Semicustom Frontend VLSI Design and Analysis of a 32-bit Brent-Kung Adder in Cadence Suite
Fuente:
arXiv
Saved in:
| Main Author: | Singh, Yashvardhan |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Design of a 64-bit SQRT-CSLA with Reduced Area and High-Speed Applications in Low Power VLSI Circuits
by: Pallavi, CH., et al.
Published: (2024)
by: Pallavi, CH., et al.
Published: (2024)
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
by: Li, Mengming, et al.
Published: (2024)
by: Li, Mengming, et al.
Published: (2024)
Online Alignment and Addition in Multi-Term Floating-Point Adders
by: Alexandridis, Kosmas, et al.
Published: (2024)
by: Alexandridis, Kosmas, et al.
Published: (2024)
AXON: An Automated Netlist Optimization Framework for High-Speed Adders
by: Yang, Tiantian, et al.
Published: (2026)
by: Yang, Tiantian, et al.
Published: (2026)
Floating Point HUB Adder for RISC-V Sargantana Processor
by: Bandera, Gerardo, et al.
Published: (2024)
by: Bandera, Gerardo, et al.
Published: (2024)
ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI
by: Sudarshan, Chetan Choppali, et al.
Published: (2023)
by: Sudarshan, Chetan Choppali, et al.
Published: (2023)
Novel Efficient Scalable QCA XOR and Full Adder Designs
by: Safaiezadeh, Behrouz, et al.
Published: (2023)
by: Safaiezadeh, Behrouz, et al.
Published: (2023)
GDR-HGNN: A Heterogeneous Graph Neural Networks Accelerator Frontend with Graph Decoupling and Recoupling
by: Xue, Runzhen, et al.
Published: (2024)
by: Xue, Runzhen, et al.
Published: (2024)
FPGA-Based Multiplier with a New Approximate Full Adder for Error-Resilient Applications
by: Ranjbar, Ali, et al.
Published: (2025)
by: Ranjbar, Ali, et al.
Published: (2025)
Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
by: Pun, Junius, et al.
Published: (2025)
by: Pun, Junius, et al.
Published: (2025)
Fast Bipartitioned Hybrid Adder Utilizing Carry Select and Carry Lookahead Logic
by: Balasubramanian, Padmanabhan, et al.
Published: (2024)
by: Balasubramanian, Padmanabhan, et al.
Published: (2024)
DiffPlace: A Conditional Diffusion Framework for Simultaneous VLSI Placement Beyond Sequential Paradigms
by: Trung, Kien Le, et al.
Published: (2025)
by: Trung, Kien Le, et al.
Published: (2025)
Multi-Partner Project: COIN-3D -- Collaborative Innovation in 3D VLSI Reliability
by: Gourdoumanis, George Rafael, et al.
Published: (2026)
by: Gourdoumanis, George Rafael, et al.
Published: (2026)
bitSMM: A bit-Serial Matrix Multiplication Accelerator
by: Antunes, Pedro, et al.
Published: (2026)
by: Antunes, Pedro, et al.
Published: (2026)
HALOC-AxA: An Area/-Energy-Efficient Approximate Adder for Image Processing Application
by: Ziad, Hasnain A., et al.
Published: (2025)
by: Ziad, Hasnain A., et al.
Published: (2025)
PrefixAgent: An LLM-Powered Design Framework for Efficient Prefix Adder Optimization
by: Zuo, Dongsheng, et al.
Published: (2025)
by: Zuo, Dongsheng, et al.
Published: (2025)
Novel Optimized Designs of Modulo $2n+1$ Adder for Quantum Computing
by: Gaur, Bhaskar, et al.
Published: (2024)
by: Gaur, Bhaskar, et al.
Published: (2024)
A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
by: Fang, Wenji, et al.
Published: (2025)
by: Fang, Wenji, et al.
Published: (2025)
SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design
by: Alvanaki, Elisavet Lydia, et al.
Published: (2025)
by: Alvanaki, Elisavet Lydia, et al.
Published: (2025)
Design of a 6-bit Threshold Inverter Quantization (TIQ) Flash Analog to Digital Converter (ADC)
by: Sarkar, Noyon Kumar, et al.
Published: (2025)
by: Sarkar, Noyon Kumar, et al.
Published: (2025)
Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation
by: Ke, Chih-Hua
Published: (2026)
by: Ke, Chih-Hua
Published: (2026)
OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark Suite
by: Shen, Shan, et al.
Published: (2025)
by: Shen, Shan, et al.
Published: (2025)
Noise-Resilient and Reduced Depth Approximate Adders for NISQ Quantum Computing
by: Gaur, Bhaskar, et al.
Published: (2024)
by: Gaur, Bhaskar, et al.
Published: (2024)
FloorSet -- a VLSI Floorplanning Dataset with Design Constraints of Real-World SoCs
by: Mallappa, Uday, et al.
Published: (2024)
by: Mallappa, Uday, et al.
Published: (2024)
Optimization of 32-bit Unsigned Division by Constants on 64-bit Targets
by: Mitsunari, Shigeo, et al.
Published: (2026)
by: Mitsunari, Shigeo, et al.
Published: (2026)
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis
by: Li, Jintao, et al.
Published: (2024)
by: Li, Jintao, et al.
Published: (2024)
Hardware-Efficient Accurate 4-bit Multiplier for Xilinx 7 Series FPGAs
by: Kida, Misaki, et al.
Published: (2025)
by: Kida, Misaki, et al.
Published: (2025)
A Logarithmic Depth Quantum Carry-Lookahead Modulo $(2^n-1)$ Adder
by: Gaur, Bhaskar, et al.
Published: (2024)
by: Gaur, Bhaskar, et al.
Published: (2024)
ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis
by: Purini, Suresh, et al.
Published: (2025)
by: Purini, Suresh, et al.
Published: (2025)
High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography
by: Tan, Weihang, et al.
Published: (2021)
by: Tan, Weihang, et al.
Published: (2021)
Hardware Generation and Exploration of Lookup Table-Based Accelerators for 1.58-bit LLM Inference
by: Geens, Robin, et al.
Published: (2026)
by: Geens, Robin, et al.
Published: (2026)
M-ANT: Efficient Low-bit Group Quantization for LLMs via Mathematically Adaptive Numerical Type
by: Hu, Weiming, et al.
Published: (2025)
by: Hu, Weiming, et al.
Published: (2025)
WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
by: Giorgi, Roberto, et al.
Published: (2025)
by: Giorgi, Roberto, et al.
Published: (2025)
Modulo-$(2^{2n}+1)$ Arithmetic via Two Parallel n-bit Residue Channels
by: Jaberipur, Ghassem, et al.
Published: (2024)
by: Jaberipur, Ghassem, et al.
Published: (2024)
M2XFP: A Metadata-Augmented Microscaling Data Format for Efficient Low-bit Quantization
by: Hu, Weiming, et al.
Published: (2026)
by: Hu, Weiming, et al.
Published: (2026)
ForgeBench: A Machine Learning Benchmark Suite and Auto-Generation Framework for Next-Generation HLS Tools
by: Wanna, Andy, et al.
Published: (2025)
by: Wanna, Andy, et al.
Published: (2025)
SPEC CPU2026: Characterization, Representativeness, and Cross-Suite Comparison
by: Li, Ruihao, et al.
Published: (2026)
by: Li, Ruihao, et al.
Published: (2026)
Beamspace Equalization for mmWave Massive MIMO: Algorithms and VLSI Implementations
by: Mirfarshbafan, Seyed Hadi, et al.
Published: (2025)
by: Mirfarshbafan, Seyed Hadi, et al.
Published: (2025)
BitROM: Weight Reload-Free CiROM Architecture Towards Billion-Parameter 1.58-bit LLM Inference
by: Zhang, Wenlun, et al.
Published: (2025)
by: Zhang, Wenlun, et al.
Published: (2025)
CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor
by: Reinwardt, Christopher, et al.
Published: (2025)
by: Reinwardt, Christopher, et al.
Published: (2025)
Similar Items
-
Design of a 64-bit SQRT-CSLA with Reduced Area and High-Speed Applications in Low Power VLSI Circuits
by: Pallavi, CH., et al.
Published: (2024) -
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
by: Li, Mengming, et al.
Published: (2024) -
Online Alignment and Addition in Multi-Term Floating-Point Adders
by: Alexandridis, Kosmas, et al.
Published: (2024) -
AXON: An Automated Netlist Optimization Framework for High-Speed Adders
by: Yang, Tiantian, et al.
Published: (2026) -
Floating Point HUB Adder for RISC-V Sargantana Processor
by: Bandera, Gerardo, et al.
Published: (2024)