Mizuhiki, R., Maeda, J., & Marumoto, S. (2025). Development of the firmware logic validation system using the FPGA accelerator.
Chicago Style (17th ed.) CitationMizuhiki, Ryugo, Junpei Maeda, and Seiya Marumoto. Development of the Firmware Logic Validation System Using the FPGA Accelerator. 2025.
MLA (9th ed.) CitationMizuhiki, Ryugo, et al. Development of the Firmware Logic Validation System Using the FPGA Accelerator. 2025.
Warning: These citations may not always be 100% accurate.