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| Autores principales: | , , , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2025
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| Materias: | |
| Acceso en línea: | https://arxiv.org/abs/2503.18543 |
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| _version_ | 1866914362337263616 |
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| author | Venieri, Emanuele Manoni, Simone Ceccolini, Gabriele Madella, Giacomo Ficarelli, Federico Gregori, Daniele Cesarini, Daniele Benini, Luca Bartolini, Andrea |
| author_facet | Venieri, Emanuele Manoni, Simone Ceccolini, Gabriele Madella, Giacomo Ficarelli, Federico Gregori, Daniele Cesarini, Daniele Benini, Luca Bartolini, Andrea |
| contents | Many RISC-V (RV) platforms and SoCs have been announced in recent years targeting the HPC sector, but only a few of them are commercially available and engineered to fit the HPC requirements. The Monte Cimone project targeted assessing their capabilities and maturity, aiming to make RISC-V a competitive choice when building a datacenter. Nowadays, Systems-on-chip (SoCs) featuring RV cores with vector extension, form factor and memory capacity suitable for HPC applications are available in the market, but it is unclear how compilers and open-source libraries can take advantage of its performance. In this paper, we describe the performance assessment of the upgrade of the Monte Cimone (MCv2) cluster with the Sophgo SG2042 processor on HPC workloads. Also adding an exploration of BLAS libraries optimization. The upgrade increases the attained node's performance by 127x on HPL DP FLOP/s and 69x on Stream Memory Bandwidth. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_18543 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Monte Cimone v2: Down the Road of RISC-V High-Performance Computers Venieri, Emanuele Manoni, Simone Ceccolini, Gabriele Madella, Giacomo Ficarelli, Federico Gregori, Daniele Cesarini, Daniele Benini, Luca Bartolini, Andrea Distributed, Parallel, and Cluster Computing Many RISC-V (RV) platforms and SoCs have been announced in recent years targeting the HPC sector, but only a few of them are commercially available and engineered to fit the HPC requirements. The Monte Cimone project targeted assessing their capabilities and maturity, aiming to make RISC-V a competitive choice when building a datacenter. Nowadays, Systems-on-chip (SoCs) featuring RV cores with vector extension, form factor and memory capacity suitable for HPC applications are available in the market, but it is unclear how compilers and open-source libraries can take advantage of its performance. In this paper, we describe the performance assessment of the upgrade of the Monte Cimone (MCv2) cluster with the Sophgo SG2042 processor on HPC workloads. Also adding an exploration of BLAS libraries optimization. The upgrade increases the attained node's performance by 127x on HPL DP FLOP/s and 69x on Stream Memory Bandwidth. |
| title | Monte Cimone v2: Down the Road of RISC-V High-Performance Computers |
| topic | Distributed, Parallel, and Cluster Computing |
| url | https://arxiv.org/abs/2503.18543 |