A Low-Power Sparse Deep Learning Accelerator with Optimized Data Reuse

Fuente: arXiv

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Bibliographic Details
Main Authors:	Hsu, Kai-Chieh, Chang, Tian-Sheuan
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2503.19639