A Low-Power Sparse Deep Learning Accelerator with Optimized Data Reuse
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arXiv
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| Auteurs principaux: | , |
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| Format: | Preprint |
| Publié: |
2025
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| _version_ | 1866912293265080320 |
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| author | Hsu, Kai-Chieh Chang, Tian-Sheuan |
| author_facet | Hsu, Kai-Chieh Chang, Tian-Sheuan |
| contents | Sparse deep learning has reduced computation significantly, but its irregular non-zero data distribution complicates the data flow and hinders data reuse, increasing on-chip SRAM access and thus power consumption of the chip. This paper addresses the aforementioned issues by maximizing data reuse to reduce SRAM access by two approaches. First, we propose Effective Index Matching (EIM), which efficiently searches and arranges non-zero operations from compressed data. Second, we propose Shared Index Data Reuse (SIDR) which coordinates the operations between Processing Elements (PEs), regularizing their SRAM data access, thereby enabling all data to be reused efficiently. Our approach reduces the access of the SRAM buffer by 86\% when compared to the previous design, SparTen. As a result, our design achieves a 2.5$\times$ improvement in power efficiency compared to state-of-the-art methods while maintaining a simpler dataflow. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_19639 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A Low-Power Sparse Deep Learning Accelerator with Optimized Data Reuse Hsu, Kai-Chieh Chang, Tian-Sheuan Hardware Architecture Sparse deep learning has reduced computation significantly, but its irregular non-zero data distribution complicates the data flow and hinders data reuse, increasing on-chip SRAM access and thus power consumption of the chip. This paper addresses the aforementioned issues by maximizing data reuse to reduce SRAM access by two approaches. First, we propose Effective Index Matching (EIM), which efficiently searches and arranges non-zero operations from compressed data. Second, we propose Shared Index Data Reuse (SIDR) which coordinates the operations between Processing Elements (PEs), regularizing their SRAM data access, thereby enabling all data to be reused efficiently. Our approach reduces the access of the SRAM buffer by 86\% when compared to the previous design, SparTen. As a result, our design achieves a 2.5$\times$ improvement in power efficiency compared to state-of-the-art methods while maintaining a simpler dataflow. |
| title | A Low-Power Sparse Deep Learning Accelerator with Optimized Data Reuse |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2503.19639 |