Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors
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arXiv
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| Hauptverfasser: | , , |
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| Format: | Preprint |
| Veröffentlicht: |
2025
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| _version_ | 1866918192602939392 |
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| author | Colagrande, Luca Jonnalagadda, Jayanth Benini, Luca |
| author_facet | Colagrande, Luca Jonnalagadda, Jayanth Benini, Luca |
| contents | Modern general-purpose accelerators integrate a large number of programmable area- and energy-efficient processing elements (PEs), to deliver high performance while meeting stringent power delivery and thermal dissipation constraints. In this context, PEs are often implemented by scalar in-order cores, which are highly sensitive to pipeline stalls. Traditional software techniques, such as loop unrolling, mitigate the issue at the cost of increased register pressure, limiting flexibility. We propose scalar chaining, a novel hardware-software solution, to address this issue without incurring the drawbacks of traditional software-only techniques. We demonstrate our solution on register-limited stencil codes, achieving >93% FPU utilizations and a 4% speedup and 10% higher energy efficiency, on average, over highly-optimized baselines. Our implementation is fully open source and performance experiments are reproducible using free software. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_20609 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors Colagrande, Luca Jonnalagadda, Jayanth Benini, Luca Hardware Architecture Modern general-purpose accelerators integrate a large number of programmable area- and energy-efficient processing elements (PEs), to deliver high performance while meeting stringent power delivery and thermal dissipation constraints. In this context, PEs are often implemented by scalar in-order cores, which are highly sensitive to pipeline stalls. Traditional software techniques, such as loop unrolling, mitigate the issue at the cost of increased register pressure, limiting flexibility. We propose scalar chaining, a novel hardware-software solution, to address this issue without incurring the drawbacks of traditional software-only techniques. We demonstrate our solution on register-limited stencil codes, achieving >93% FPU utilizations and a 4% speedup and 10% higher energy efficiency, on average, over highly-optimized baselines. Our implementation is fully open source and performance experiments are reproducible using free software. |
| title | Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2503.20609 |