CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device
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arXiv
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| Autores principales: | , , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2025
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| Materias: | |
| Acceso en línea: | |
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| _version_ | 1866910897638735872 |
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| author | and, Yan-Cheng Guo Chang, Tian-Sheuan Lin, Chih-Sheng Chiou, Bo-Cheng Lai, Chih-Ming Sheu, Shyh-Shyuan Lo, Wei-Chung Chang, Shih-Chieh |
| author_facet | and, Yan-Cheng Guo Chang, Tian-Sheuan Lin, Chih-Sheng Chiou, Bo-Cheng Lai, Chih-Ming Sheu, Shyh-Shyuan Lo, Wei-Chung Chang, Shih-Chieh |
| contents | Computing-in-memory (CIM) is renowned in deep learning due to its high energy efficiency resulting from highly parallel computing with minimal data movement. However, current SRAM-based CIM designs suffer from long latency for loading weight or feature maps from DRAM for large AI models. Moreover, previous SRAM-based CIM architectures lack end-to-end model inference. To address these issues, this paper proposes CIMR-V, an end-to-end CIM accelerator with RISC-V that incorporates CIM layer fusion, convolution/max pooling pipeline, and weight fusion, resulting in an 85.14\% reduction in latency for the keyword spotting model. Furthermore, the proposed CIM-type instructions facilitate end-to-end AI model inference and full stack flow, effectively synergizing the high energy efficiency of CIM and the high programmability of RISC-V. Implemented using TSMC 28nm technology, the proposed design achieves an energy efficiency of 3707.84 TOPS/W and 26.21 TOPS at 50 MHz. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_22072 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device and, Yan-Cheng Guo Chang, Tian-Sheuan Lin, Chih-Sheng Chiou, Bo-Cheng Lai, Chih-Ming Sheu, Shyh-Shyuan Lo, Wei-Chung Chang, Shih-Chieh Hardware Architecture Computing-in-memory (CIM) is renowned in deep learning due to its high energy efficiency resulting from highly parallel computing with minimal data movement. However, current SRAM-based CIM designs suffer from long latency for loading weight or feature maps from DRAM for large AI models. Moreover, previous SRAM-based CIM architectures lack end-to-end model inference. To address these issues, this paper proposes CIMR-V, an end-to-end CIM accelerator with RISC-V that incorporates CIM layer fusion, convolution/max pooling pipeline, and weight fusion, resulting in an 85.14\% reduction in latency for the keyword spotting model. Furthermore, the proposed CIM-type instructions facilitate end-to-end AI model inference and full stack flow, effectively synergizing the high energy efficiency of CIM and the high programmability of RISC-V. Implemented using TSMC 28nm technology, the proposed design achieves an energy efficiency of 3707.84 TOPS/W and 26.21 TOPS at 50 MHz. |
| title | CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2503.22072 |