Scalable Superconducting Nanowire Memory Array with Row-Column Addressing
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arXiv
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| Autori principali: | , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| author | Medeiros, Owen Castellani, Matteo Karam, Valentin Foster, Reed Simon, Alejandro Incalza, Francesca Butters, Brenden Colangelo, Marco Berggren, Karl K |
| author_facet | Medeiros, Owen Castellani, Matteo Karam, Valentin Foster, Reed Simon, Alejandro Incalza, Francesca Butters, Brenden Colangelo, Marco Berggren, Karl K |
| contents | Developing ultra-low-energy superconducting computing and fault-tolerant quantum computing will require scalable superconducting memory. While conventional superconducting logic-based memory cells have facilitated early demonstrations, their large footprint poses a significant barrier to scaling. Nanowire-based superconducting memory cells offer a compact alternative, but high error rates have hindered their integration into large arrays. In this work, we present a superconducting nanowire memory array designed for scalable row-column operation, achieving a functional density of 2.6$\,$Mb/cm$^{2}$. The array operates at $1.3\,$K, where we implement and characterize multi-flux quanta state storage and destructive readout. By optimizing write and read pulse sequences, we minimize bit errors while maximizing operational margins in a $4\times 4$ array. Circuit-level simulations further elucidate the memory cell's dynamics, providing insight into performance limits and stability under varying pulse amplitudes. We experimentally demonstrate stable memory operation with a minimum bit error rate of $10^{-5}$. These results suggest a promising path for scaling superconducting nanowire memories to high-density architectures, offering a foundation for energy-efficient memory in superconducting electronics. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2503_22897 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Scalable Superconducting Nanowire Memory Array with Row-Column Addressing Medeiros, Owen Castellani, Matteo Karam, Valentin Foster, Reed Simon, Alejandro Incalza, Francesca Butters, Brenden Colangelo, Marco Berggren, Karl K Applied Physics Developing ultra-low-energy superconducting computing and fault-tolerant quantum computing will require scalable superconducting memory. While conventional superconducting logic-based memory cells have facilitated early demonstrations, their large footprint poses a significant barrier to scaling. Nanowire-based superconducting memory cells offer a compact alternative, but high error rates have hindered their integration into large arrays. In this work, we present a superconducting nanowire memory array designed for scalable row-column operation, achieving a functional density of 2.6$\,$Mb/cm$^{2}$. The array operates at $1.3\,$K, where we implement and characterize multi-flux quanta state storage and destructive readout. By optimizing write and read pulse sequences, we minimize bit errors while maximizing operational margins in a $4\times 4$ array. Circuit-level simulations further elucidate the memory cell's dynamics, providing insight into performance limits and stability under varying pulse amplitudes. We experimentally demonstrate stable memory operation with a minimum bit error rate of $10^{-5}$. These results suggest a promising path for scaling superconducting nanowire memories to high-density architectures, offering a foundation for energy-efficient memory in superconducting electronics. |
| title | Scalable Superconducting Nanowire Memory Array with Row-Column Addressing |
| topic | Applied Physics |
| url | https://arxiv.org/abs/2503.22897 |