:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Authors:	Shi, Rui, Ogrenci, Seda
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	https://arxiv.org/abs/2504.00206
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
by: Li, Runkai, et al.
Published: (2025)

Stream-HLS: Towards Automatic Dataflow Acceleration
by: Basalama, Suhail, et al.
Published: (2025)

HLStrans: Dataset for C-to-HLS Hardware Code Synthesis
by: Zou, Qingyun, et al.
Published: (2025)

MING: An Automated CNN-to-Edge MLIR HLS framework
by: Bi, Jiahong, et al.
Published: (2026)

ForgeBench: A Machine Learning Benchmark Suite and Auto-Generation Framework for Next-Generation HLS Tools
by: Wanna, Andy, et al.
Published: (2025)

Analyzing the capabilities of HLS and RTL tools in the design of an FPGA Montgomery Multiplier
by: Ifrim, Rares, et al.
Published: (2025)

AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs
by: Ahmed, Md Rubel, et al.
Published: (2024)

Iceberg: Enhancing HLS Modeling with Synthetic Data
by: Ding, Zijian, et al.
Published: (2025)

R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State Edges
by: Metz, David, et al.
Published: (2024)

DAE4HLS: Exposing Memory-Level Parallelism for High-Level Synthesis using Explicit Decoupling
by: Metz, David, et al.
Published: (2026)

Designing Reconfigurable Interconnection Network of Heterogeneous Chiplets Using Kalman Filter
by: Biglari, Siamak, et al.
Published: (2024)

Characterization of Real Communication Patterns and Congestion Dynamics in HPC Interconnection Networks
by: de La Rosa, Miguel Sánchez, et al.
Published: (2026)

On the Impact of Intra-node Communication in the Performance of Supercomputer and Data Center Interconnection Networks
by: Tarraga-Moreno, Joaquin, et al.
Published: (2025)

SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators
by: Brignone, Giovanni, et al.
Published: (2024)

A Linear-Time Algorithm for Steady-State Analysis of Electromigration in General Interconnects
by: Shohel, Mohammad Abdullah Al, et al.
Published: (2021)

Efficient Task Transfer for HLS DSE
by: Ding, Zijian, et al.
Published: (2024)

A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
by: Brignone, Giovanni, et al.
Published: (2023)

PICNIC: Silicon Photonic Interconnected Chiplets with Computational Network and In-memory Computing for LLM Inference Acceleration
by: Chong, Yue Jiet, et al.
Published: (2025)

Scalable and Efficient Intra- and Inter-node Interconnection Networks for Post-Exascale Supercomputers and Data centers
by: Tarraga-Moreno, Joaquin, et al.
Published: (2025)

Link Quality Aware Pathfinding for Chiplet Interconnects
by: Yen, Aaron, et al.
Published: (2026)

PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies
by: Iff, Patrick, et al.
Published: (2025)

Neuromorphic Processor Employing FPGA Technology with Universal Interconnections
by: Harlikar, Pracheta, et al.
Published: (2025)

Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs
by: Wang, Xiaoke, et al.
Published: (2026)

ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesis
by: Peng, Zedong, et al.
Published: (2025)

A Hybrid Delay Model for Interconnected Multi-Input Gates
by: Ferdowsi, Arman, et al.
Published: (2024)

HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks
by: Abi-Karam, Stefan, et al.
Published: (2025)

MPM-LLM4DSE: Reaching the Pareto Frontier in HLS with Multimodal Learning and LLM-Driven Exploration
by: Xu, Lei, et al.
Published: (2026)

Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
by: Gai, Jiahao, et al.
Published: (2025)

METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators
by: Wang, Zhao, et al.
Published: (2021)

PipeOrgan: Efficient Inter-operation Pipelining with Flexible Spatial Organization and Interconnects
by: Garg, Raveesh, et al.
Published: (2024)

LACIN: Linearly Arranged Complete Interconnection Networks
by: Beivide, Ramón, et al.
Published: (2026)

relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
by: Rogenmoser, Michael, et al.
Published: (2025)

Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
by: Zhao, Hongwei, et al.
Published: (2025)

ChipLight: Cross-Layer Optimization of Chiplet Design with Optical Interconnects for LLM Training
by: Bai, Kangbo, et al.
Published: (2026)

Best Practices for Large Load Interconnections: A North American Perspective on Data Centers
by: Zahedi, Rafi, et al.
Published: (2026)

Hardware.jl - An MLIR-based Julia HLS Flow (Work in Progress)
by: Short, Benedict, et al.
Published: (2025)

The BrainScaleS-2 multi-chip system: Interconnecting continuous-time neuromorphic compute substrates
by: Ilmberger, Joscha, et al.
Published: (2025)

Switch-Less Dragonfly on Wafers: A Scalable Interconnection Architecture based on Wafer-Scale Integration
by: Feng, Yinxiao, et al.
Published: (2024)

FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design
by: Zhang, Jiahao, et al.
Published: (2026)

Special Session: Sustainable Deployment of Deep Neural Networks on Non-Volatile Compute-in-Memory Accelerators
by: Qin, Yifan, et al.
Published: (2025)