Versatile silicon integrated photonic processor: a reconfigurable solution for next-generation AI clusters
Fuente:
arXiv
Salvato in:
| Autori principali: | , , , , , , , , , , , , , , |
|---|---|
| Natura: | Preprint |
| Pubblicazione: |
2025
|
| Soggetti: | |
| Accesso online: | |
| Tags: |
Aggiungi Tag
Nessun Tag, puoi essere il primo ad aggiungerne!!
|
| _version_ | 1866911135363497984 |
|---|---|
| author | Zhu, Ying Liu, Yifan Yang, Xinyu Liu, Kailai Hua, Xin Luo, Ming Liu, Jia Chang, Siyao Zhang, Shengxiang Wu, Miao Wang, Zhicheng Zhang, Hongguang Chen, Daigao Xiao, Xi Yu, Shaohua |
| author_facet | Zhu, Ying Liu, Yifan Yang, Xinyu Liu, Kailai Hua, Xin Luo, Ming Liu, Jia Chang, Siyao Zhang, Shengxiang Wu, Miao Wang, Zhicheng Zhang, Hongguang Chen, Daigao Xiao, Xi Yu, Shaohua |
| contents | The Artificial Intelligence models pose serious challenges in intensive computing and high-bandwidth communication for conventional electronic circuit-based computing clusters. Silicon photonic technologies, owing to their high speed, low latency, large bandwidth, and complementary metal-oxide-semiconductor compatibility, have been widely implemented for data transfer and actively explored as photonic neural networks in AI clusters. However, current silicon photonic integrated chips lack adaptability for multifuncional use and hardware-software systematic coordination. Here, we develop a reconfigurable silicon photonic processor with $40$ programmable unit cells integrating over $160$ component, which, to the best of our knowledge, is the first to realize diverse functions with a chip for AI clusters, from computing acceleration and signal processing to network swtiching and secure encryption. Through a self-developed automated testing, compilation, and tuning framework to the processor without in-network monitoring photodetectors, we implement $4\times4$ dual-direction unitary and $3\times3$ uni-direction non-unitary matrix multiplications, neural networks for image recognition, micro-ring modulator wavelength locking, $4\times4$ photonic channel switching , and silicon photonic physical unclonable functions. This optoelectronic processing system, incorporating the photonic processor and its software stack, paves the way for both advanced photonic system-on-chip design and the construction of photo-electronic AI clusters. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2504_01463 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Versatile silicon integrated photonic processor: a reconfigurable solution for next-generation AI clusters Zhu, Ying Liu, Yifan Yang, Xinyu Liu, Kailai Hua, Xin Luo, Ming Liu, Jia Chang, Siyao Zhang, Shengxiang Wu, Miao Wang, Zhicheng Zhang, Hongguang Chen, Daigao Xiao, Xi Yu, Shaohua Optics Hardware Architecture The Artificial Intelligence models pose serious challenges in intensive computing and high-bandwidth communication for conventional electronic circuit-based computing clusters. Silicon photonic technologies, owing to their high speed, low latency, large bandwidth, and complementary metal-oxide-semiconductor compatibility, have been widely implemented for data transfer and actively explored as photonic neural networks in AI clusters. However, current silicon photonic integrated chips lack adaptability for multifuncional use and hardware-software systematic coordination. Here, we develop a reconfigurable silicon photonic processor with $40$ programmable unit cells integrating over $160$ component, which, to the best of our knowledge, is the first to realize diverse functions with a chip for AI clusters, from computing acceleration and signal processing to network swtiching and secure encryption. Through a self-developed automated testing, compilation, and tuning framework to the processor without in-network monitoring photodetectors, we implement $4\times4$ dual-direction unitary and $3\times3$ uni-direction non-unitary matrix multiplications, neural networks for image recognition, micro-ring modulator wavelength locking, $4\times4$ photonic channel switching , and silicon photonic physical unclonable functions. This optoelectronic processing system, incorporating the photonic processor and its software stack, paves the way for both advanced photonic system-on-chip design and the construction of photo-electronic AI clusters. |
| title | Versatile silicon integrated photonic processor: a reconfigurable solution for next-generation AI clusters |
| topic | Optics Hardware Architecture |
| url | https://arxiv.org/abs/2504.01463 |