MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors

Fuente: arXiv

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Bibliographic Details
Main Authors:	You, Dean, Jiang, Jieyu, Wang, Xiaoxuan, Du, Yushu, Tan, Zhihang, Xu, Wenbo, Wang, Hui, Guan, Jiapeng, Wang, Zhenyuan, Wei, Ran, Zhao, Shuai, Jiang, Zhe
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2504.01582