Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design
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arXiv
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| Format: | Preprint |
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2025
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| author | Ho, Chia-Tung Gong, Jing Bai, Yunsheng Deng, Chenhui Ren, Haoxing Khailany, Brucek |
| author_facet | Ho, Chia-Tung Gong, Jing Bai, Yunsheng Deng, Chenhui Ren, Haoxing Khailany, Brucek |
| contents | Hardware design presents numerous challenges stemming from its complexity and advancing technologies. These challenges result in longer turn-around-time (TAT) for optimizing performance, power, area, and cost (PPAC) during synthesis, verification, physical design, and reliability loops. Large Language Models (LLMs) have shown remarkable capacity to comprehend and generate natural language at a massive scale, leading to many potential applications and benefits across various domains. Successful LLM-based agents for hardware design can drastically reduce TAT, leading to faster product cycles, lower costs, improved design reliability and reduced risk of costly errors. In this work, we propose a unified framework, Marco, that integrates configurable graph-based task solving with multi-modality and multi-AI agents for chip design by leveraging the natural language and reasoning abilities with collaborative toolkits. Lastly, we demonstrate promising performance, productivity, and efficiency of LLM agents by leveraging the Marco framework on layout optimization, Verilog/design rule checker (DRC) coding, and timing analysis tasks. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2504_01962 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design Ho, Chia-Tung Gong, Jing Bai, Yunsheng Deng, Chenhui Ren, Haoxing Khailany, Brucek Hardware Architecture Hardware design presents numerous challenges stemming from its complexity and advancing technologies. These challenges result in longer turn-around-time (TAT) for optimizing performance, power, area, and cost (PPAC) during synthesis, verification, physical design, and reliability loops. Large Language Models (LLMs) have shown remarkable capacity to comprehend and generate natural language at a massive scale, leading to many potential applications and benefits across various domains. Successful LLM-based agents for hardware design can drastically reduce TAT, leading to faster product cycles, lower costs, improved design reliability and reduced risk of costly errors. In this work, we propose a unified framework, Marco, that integrates configurable graph-based task solving with multi-modality and multi-AI agents for chip design by leveraging the natural language and reasoning abilities with collaborative toolkits. Lastly, we demonstrate promising performance, productivity, and efficiency of LLM agents by leveraging the Marco framework on layout optimization, Verilog/design rule checker (DRC) coding, and timing analysis tasks. |
| title | Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2504.01962 |