Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design
Fuente:
arXiv
Guardado en:
| Autores principales: | Ho, Chia-Tung, Gong, Jing, Bai, Yunsheng, Deng, Chenhui, Ren, Haoxing, Khailany, Brucek |
|---|---|
| Formato: | Preprint |
| Publicado: |
2025
|
| Materias: | |
| Acceso en línea: | |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares
Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
por: Pinckney, Nathaniel, et al.
Publicado: (2025)
por: Pinckney, Nathaniel, et al.
Publicado: (2025)
GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation
por: Kochar, Dimple Vijay, et al.
Publicado: (2026)
por: Kochar, Dimple Vijay, et al.
Publicado: (2026)
ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
por: Deng, Chenhui, et al.
Publicado: (2024)
por: Deng, Chenhui, et al.
Publicado: (2024)
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation
por: Pinckney, Nathaniel, et al.
Publicado: (2024)
por: Pinckney, Nathaniel, et al.
Publicado: (2024)
ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
por: Deng, Chenhui, et al.
Publicado: (2026)
por: Deng, Chenhui, et al.
Publicado: (2026)
Large Language Model (LLM) for Standard Cell Layout Design Optimization
por: Ho, Chia-Tung, et al.
Publicado: (2024)
por: Ho, Chia-Tung, et al.
Publicado: (2024)
FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures
por: Bai, Yunsheng, et al.
Publicado: (2025)
por: Bai, Yunsheng, et al.
Publicado: (2025)
DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent
por: Chang, Chen-Chia, et al.
Publicado: (2024)
por: Chang, Chen-Chia, et al.
Publicado: (2024)
FVRuleLearner: Operator-Level Reasoning Tree (OP-Tree)-Based Rules Learning for Formal Verification
por: Wan, Lily Jiaxin, et al.
Publicado: (2026)
por: Wan, Lily Jiaxin, et al.
Publicado: (2026)
FGMP: Fine-Grained Mixed-Precision Weight and Activation Quantization for Hardware-Accelerated LLM Inference
por: Hooper, Coleman, et al.
Publicado: (2025)
por: Hooper, Coleman, et al.
Publicado: (2025)
Learning to Compare Hardware Designs for High-Level Synthesis
por: Bai, Yunsheng, et al.
Publicado: (2024)
por: Bai, Yunsheng, et al.
Publicado: (2024)
Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems
por: Yu, Zhongzhi, et al.
Publicado: (2025)
por: Yu, Zhongzhi, et al.
Publicado: (2025)
GauRast: Enhancing GPU Triangle Rasterizers to Accelerate 3D Gaussian Splatting
por: Li, Sixu, et al.
Publicado: (2025)
por: Li, Sixu, et al.
Publicado: (2025)
PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
por: Zhao, Yujie, et al.
Publicado: (2025)
por: Zhao, Yujie, et al.
Publicado: (2025)
Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC
por: Yu, Cunxi, et al.
Publicado: (2026)
por: Yu, Cunxi, et al.
Publicado: (2026)
ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation
por: Deng, Chenhui, et al.
Publicado: (2025)
por: Deng, Chenhui, et al.
Publicado: (2025)
FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware
por: Kang, Minwoo, et al.
Publicado: (2024)
por: Kang, Minwoo, et al.
Publicado: (2024)
RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
por: Tsai, Yun-Da, et al.
Publicado: (2023)
por: Tsai, Yun-Da, et al.
Publicado: (2023)
Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design
por: Pan, Tianwei, et al.
Publicado: (2025)
por: Pan, Tianwei, et al.
Publicado: (2025)
VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
por: Ho, Chia-Tung, et al.
Publicado: (2024)
por: Ho, Chia-Tung, et al.
Publicado: (2024)
Taming Performance Variability caused by Client-Side Hardware Configuration
por: Antoniou, Georgia, et al.
Publicado: (2024)
por: Antoniou, Georgia, et al.
Publicado: (2024)
FPGA-Optimized Hardware Accelerator for Fast Fourier Transform and Singular Value Decomposition in AI
por: Ding, Hong, et al.
Publicado: (2025)
por: Ding, Hong, et al.
Publicado: (2025)
AutoPDR: Circuit-Aware Solver Configuration Prediction for Hardware Model Checking
por: Hu, Guangyu, et al.
Publicado: (2026)
por: Hu, Guangyu, et al.
Publicado: (2026)
Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning
por: Kanda, R., et al.
Publicado: (2026)
por: Kanda, R., et al.
Publicado: (2026)
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
por: Fu, Lik Tung, et al.
Publicado: (2026)
por: Fu, Lik Tung, et al.
Publicado: (2026)
Dynamic Power Control in a Hardware Neural Network with Error-Configurable MAC Units
por: Ghaderi, Maedeh, et al.
Publicado: (2024)
por: Ghaderi, Maedeh, et al.
Publicado: (2024)
Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware
por: Kanda, R., et al.
Publicado: (2026)
por: Kanda, R., et al.
Publicado: (2026)
SQ-DM: Accelerating Diffusion Models with Aggressive Quantization and Temporal Sparsity
por: Fan, Zichen, et al.
Publicado: (2025)
por: Fan, Zichen, et al.
Publicado: (2025)
Spec2Cov: An Agentic Framework for Code Coverage Closure of Digital Hardware Designs
por: Lowe, Sean, et al.
Publicado: (2026)
por: Lowe, Sean, et al.
Publicado: (2026)
"Test, Build, Deploy" -- A CI/CD Framework for Open-Source Hardware Designs
por: Deutschbein, Calvin, et al.
Publicado: (2025)
por: Deutschbein, Calvin, et al.
Publicado: (2025)
Invited Paper: FEMU: An Open-Source and Configurable Emulation Framework for Prototyping TinyAI Heterogeneous Systems
por: Machetti, Simone, et al.
Publicado: (2025)
por: Machetti, Simone, et al.
Publicado: (2025)
Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification
por: Gadde, Deepak Narayan, et al.
Publicado: (2025)
por: Gadde, Deepak Narayan, et al.
Publicado: (2025)
elasticAI.explorer: Towards a Unified End-to-End Framework for Hardware-Aware Neural Architecture Search
por: Maman, Natalie, et al.
Publicado: (2026)
por: Maman, Natalie, et al.
Publicado: (2026)
Accelerating PageRank Algorithmic Tasks with a new Programmable Hardware Architecture
por: Chowdhury, Md Rownak Hossain, et al.
Publicado: (2024)
por: Chowdhury, Md Rownak Hossain, et al.
Publicado: (2024)
Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads
por: Popovici, Doru Thom, et al.
Publicado: (2025)
por: Popovici, Doru Thom, et al.
Publicado: (2025)
AiEDA: Agentic AI Design Framework for Digital ASIC System Design
por: Patra, Aditya, et al.
Publicado: (2024)
por: Patra, Aditya, et al.
Publicado: (2024)
Intelligent OPC Engineer Assistant for Semiconductor Manufacturing
por: Chen, Guojin, et al.
Publicado: (2024)
por: Chen, Guojin, et al.
Publicado: (2024)
A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
por: Yunusoglu, Aybars, et al.
Publicado: (2026)
por: Yunusoglu, Aybars, et al.
Publicado: (2026)
TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
por: Tozlu, Yavuz Selim, et al.
Publicado: (2026)
por: Tozlu, Yavuz Selim, et al.
Publicado: (2026)
ONNX-to-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs
por: Manca, Federico, et al.
Publicado: (2024)
por: Manca, Federico, et al.
Publicado: (2024)
Ejemplares similares
-
Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
por: Pinckney, Nathaniel, et al.
Publicado: (2025) -
GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation
por: Kochar, Dimple Vijay, et al.
Publicado: (2026) -
ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
por: Deng, Chenhui, et al.
Publicado: (2024) -
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation
por: Pinckney, Nathaniel, et al.
Publicado: (2024) -
ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
por: Deng, Chenhui, et al.
Publicado: (2026)