Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6
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arXiv
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| Auteurs principaux: | , , , |
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| Format: | Preprint |
| Publié: |
2025
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| _version_ | 1866915224578162688 |
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| author | Laghi, Umberto Manoni, Simone Parisi, Emanuele Bartolini, Andrea |
| author_facet | Laghi, Umberto Manoni, Simone Parisi, Emanuele Bartolini, Andrea |
| contents | In this work, we present the design and evaluation of a Processor Tracing System compliant with the RISC-V Efficient Trace specification for Instruction Branch Tracing. We integrate our system into the host domain of a state-of-the-art edge architecture based on CVA6. The proposed Tracing System introduces a total overhead of 9.2% in terms of resource utilization on a Xilinx VCU118 FPGA on the CVA6 subsystem while achieving an average compression rate of 95.1% on platform-specific tests, compared to tracing each full opcode instruction. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2504_01972 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6 Laghi, Umberto Manoni, Simone Parisi, Emanuele Bartolini, Andrea Hardware Architecture In this work, we present the design and evaluation of a Processor Tracing System compliant with the RISC-V Efficient Trace specification for Instruction Branch Tracing. We integrate our system into the host domain of a state-of-the-art edge architecture based on CVA6. The proposed Tracing System introduces a total overhead of 9.2% in terms of resource utilization on a Xilinx VCU118 FPGA on the CVA6 subsystem while achieving an average compression rate of 95.1% on platform-specific tests, compared to tracing each full opcode instruction. |
| title | Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6 |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2504.01972 |