Cover Image

NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Yang, Kaiyuan, Ouyang, Huang, Wang, Xinyi, Lu, Bingjie, Wang, Yanbo, Abhayaratne, Charith, Li, Sizhao, Jin, Long, Deng, Tiantai
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Artificial Intelligence
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

VeriPy -- A New Python-Based Approach for SDR Pipelined/Unrolled Hardware Accelerator Generation
by: Zhao, Yuqin, et al.
Published: (2025)

GenAI-Driven Approach to RISC-V Supply Chain Exploration
by: Petrovic, Nenad, et al.
Published: (2026)

Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU
by: Pu, Huanzhi, et al.
Published: (2025)

All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification
by: Gadde, Deepak Narayan, et al.
Published: (2024)

Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE
by: Ahmad, Adeel, et al.
Published: (2025)

GenDRAM:Hardware-Software Co-Design of General Platform in DRAM
by: Lu, Tsung-Han, et al.
Published: (2026)

Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach
by: Pouget, Stéphane, et al.
Published: (2024)

A Power-Efficient Hardware Implementation of L-Mul
by: Chen, Ruiqi, et al.
Published: (2024)

From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design
by: Fu, Weimin, et al.
Published: (2026)

EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning
by: Hu, Guangyu, et al.
Published: (2026)

Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators
by: Tanaka, Izumi, et al.
Published: (2026)

Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design
by: Ho, Chia-Tung, et al.
Published: (2025)

HLStrans: Dataset for C-to-HLS Hardware Code Synthesis
by: Zou, Qingyun, et al.
Published: (2025)

OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
by: Sarkar, Rishov, et al.
Published: (2025)

An Efficient Hardware Implementation of Elliptic Curve Point Multiplication over $GF(2^m)$ on FPGA
by: Kumari, Ruby, et al.
Published: (2025)

Learning to Compare Hardware Designs for High-Level Synthesis
by: Bai, Yunsheng, et al.
Published: (2024)

GenPairX: A Hardware-Algorithm Co-Designed Accelerator for Paired-End Read Mapping
by: Eudine, Julien, et al.
Published: (2026)

Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning
by: Kanda, R., et al.
Published: (2026)

A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs
by: Dang, Peng, et al.
Published: (2024)

An Efficient Sparse Hardware Accelerator for Spike-Driven Transformer
by: Li, Zhengke, et al.
Published: (2025)

ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
by: Li, Runkai, et al.
Published: (2025)

Memory-Guided Unified Hardware Accelerator for Mixed-Precision Scientific Computing
by: Wang, Chuanzhen, et al.
Published: (2026)

SRAM Based Digital Custom Compute Engine for Improved Area Efficiency of AI Hardware
by: Dhakad, Narendra Singh, et al.
Published: (2026)

FPGA-Optimized Hardware Accelerator for Fast Fourier Transform and Singular Value Decomposition in AI
by: Ding, Hong, et al.
Published: (2025)

Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware
by: Kanda, R., et al.
Published: (2026)

HLSPilot: LLM-based High-Level Synthesis
by: Xiong, Chenwei, et al.
Published: (2024)

Dynamic Loop Fusion in High-Level Synthesis
by: Szafarczyk, Robert, et al.
Published: (2025)

METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators
by: Wang, Zhao, et al.
Published: (2021)

Sustainable Hardware Specialization
by: Dangi, Pranav, et al.
Published: (2024)

MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
by: You, Dean, et al.
Published: (2025)

CATransformers: Carbon Aware Transformers Through Joint Model-Hardware Optimization
by: Wang, Irene, et al.
Published: (2025)

SD-Acc: Accelerating Stable Diffusion through Phase-aware Sampling and Hardware Co-Optimizations
by: Wang, Zhican, et al.
Published: (2025)

AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging
by: Lyu, Hongqin, et al.
Published: (2025)

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
by: Zhong, Yang, et al.
Published: (2025)

System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints
by: Liao, Yuchao, et al.
Published: (2024)

DAE4HLS: Exposing Memory-Level Parallelism for High-Level Synthesis using Explicit Decoupling
by: Metz, David, et al.
Published: (2026)

Harmonia: Algorithm-Hardware Co-Design for Memory- and Compute-Efficient BFP-based LLM Inference
by: Wang, Xinyu, et al.
Published: (2026)

Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification
by: Gadde, Deepak Narayan, et al.
Published: (2025)

elasticAI.explorer: Towards a Unified End-to-End Framework for Hardware-Aware Neural Architecture Search
by: Maman, Natalie, et al.
Published: (2026)

Hardware Implementation of Soft Mapper/Demappers in Iterative EP-based Receivers
by: Schilling, Ian Fischer, et al.
Published: (2024)