ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
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arXiv
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| Autores principales: | , , , , , |
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| Formato: | Preprint |
| Publicado: |
2025
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| _version_ | 1866915232312459264 |
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| author | Petrolo, Vincenzo Guella, Flavia Caon, Michele Schiavone, Pasquale Davide Masera, Guido Martina, Maurizio |
| author_facet | Petrolo, Vincenzo Guella, Flavia Caon, Michele Schiavone, Pasquale Davide Masera, Guido Martina, Maurizio |
| contents | Modern data-driven applications expose limitations of von Neumann architectures - extensive data movement, low throughput, and poor energy efficiency. Accelerators improve performance but lack flexibility and require data transfers. Existing compute in- and near-memory solutions mitigate these issues but face usability challenges due to data placement constraints. We propose a novel cache architecture that doubles as a tightly-coupled compute-near-memory coprocessor. Our RISC-V cache controller executes custom instructions from the host CPU using vector operations dispatched to near-memory vector processing units within the cache memory subsystem. This architecture abstracts memory synchronization and data mapping from application software while offering software-based Instruction Set Architecture extensibility. Our implementation shows $30\times$ to $84\times$ performance improvement when operating on 8-bit data over the same system with a traditional cache when executing a worst-case 32-bit CNN workload, with only $41.3\%$ area overhead. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2504_02533 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions Petrolo, Vincenzo Guella, Flavia Caon, Michele Schiavone, Pasquale Davide Masera, Guido Martina, Maurizio Hardware Architecture Modern data-driven applications expose limitations of von Neumann architectures - extensive data movement, low throughput, and poor energy efficiency. Accelerators improve performance but lack flexibility and require data transfers. Existing compute in- and near-memory solutions mitigate these issues but face usability challenges due to data placement constraints. We propose a novel cache architecture that doubles as a tightly-coupled compute-near-memory coprocessor. Our RISC-V cache controller executes custom instructions from the host CPU using vector operations dispatched to near-memory vector processing units within the cache memory subsystem. This architecture abstracts memory synchronization and data mapping from application software while offering software-based Instruction Set Architecture extensibility. Our implementation shows $30\times$ to $84\times$ performance improvement when operating on 8-bit data over the same system with a traditional cache when executing a worst-case 32-bit CNN workload, with only $41.3\%$ area overhead. |
| title | ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2504.02533 |