WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
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arXiv
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| Main Authors: | , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866910904119984128 |
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| author | Giorgi, Roberto Mariotti, Gianfranco |
| author_facet | Giorgi, Roberto Mariotti, Gianfranco |
| contents | WebRISC-V is a web-based educational tool designed to simulate the pipelined execution of assembly programs according to the RV64IM specifications (64-bit RISC-V processor). The tool allows users to investigate pipeline stalls, understand the internal state of pipeline architectural blocks, and visualize the cycle-by-cycle execution of instructions. WebRISC-V executes directly in a web browser, providing a detailed pipeline execution for RISC-V processors. This paper describes the features of WebRISC-V, compares it with similar tools, and provides an example of its usage in investigating the pipeline. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2504_03722 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes Giorgi, Roberto Mariotti, Gianfranco Hardware Architecture WebRISC-V is a web-based educational tool designed to simulate the pipelined execution of assembly programs according to the RV64IM specifications (64-bit RISC-V processor). The tool allows users to investigate pipeline stalls, understand the internal state of pipeline architectural blocks, and visualize the cycle-by-cycle execution of instructions. WebRISC-V executes directly in a web browser, providing a detailed pipeline execution for RISC-V processors. This paper describes the features of WebRISC-V, compares it with similar tools, and provides an example of its usage in investigating the pipeline. |
| title | WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2504.03722 |