Learning Cache Coherence Traffic for NoC Routing Design
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arXiv
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| Autores principales: | , , |
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| Formato: | Preprint |
| Publicado: |
2025
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| Acceso en línea: | |
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| _version_ | 1866916773726519296 |
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| author | Xiong, Guochu Luo, Xiangzhong Liu, Weichen |
| author_facet | Xiong, Guochu Luo, Xiangzhong Liu, Weichen |
| contents | The rapid growth of multi-core systems highlights the need for efficient Network-on-Chip (NoC) design to ensure seamless communication. Cache coherence, essential for data consistency, substantially reduces task computation time by enabling data sharing among caches. As a result, routing serves two roles: facilitating data sharing (influenced by topology) and managing NoC-level communication. However, cache coherence is often overlooked in routing, causing mismatches between design expectations and evaluation outcomes. Two main challenges are the lack of specialized tools to assess cache coherence's impact and the neglect of topology selection in routing. In this work, we propose a cache coherence-aware routing approach with integrated topology selection, guided by our Cache Coherence Traffic Analyzer (CCTA). Our method achieves up to 10.52% lower packet latency, 55.51% faster execution time, and 49.02% total energy savings, underscoring the critical role of cache coherence in NoC design and enabling effective co-design. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2504_04005 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Learning Cache Coherence Traffic for NoC Routing Design Xiong, Guochu Luo, Xiangzhong Liu, Weichen Hardware Architecture Networking and Internet Architecture The rapid growth of multi-core systems highlights the need for efficient Network-on-Chip (NoC) design to ensure seamless communication. Cache coherence, essential for data consistency, substantially reduces task computation time by enabling data sharing among caches. As a result, routing serves two roles: facilitating data sharing (influenced by topology) and managing NoC-level communication. However, cache coherence is often overlooked in routing, causing mismatches between design expectations and evaluation outcomes. Two main challenges are the lack of specialized tools to assess cache coherence's impact and the neglect of topology selection in routing. In this work, we propose a cache coherence-aware routing approach with integrated topology selection, guided by our Cache Coherence Traffic Analyzer (CCTA). Our method achieves up to 10.52% lower packet latency, 55.51% faster execution time, and 49.02% total energy savings, underscoring the critical role of cache coherence in NoC design and enabling effective co-design. |
| title | Learning Cache Coherence Traffic for NoC Routing Design |
| topic | Hardware Architecture Networking and Internet Architecture |
| url | https://arxiv.org/abs/2504.04005 |