FETTA: Flexible and Efficient Hardware Accelerator for Tensorized Neural Network Training
Fuente:
arXiv
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| Main Authors: | Lu, Jinming, Tian, Jiayi, Li, Hai, Young, Ian, Zhang, Zheng |
|---|---|
| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | |
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