Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
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arXiv
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| Format: | Preprint |
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2025
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| author | Cammarata, Danilo Perotti, Matteo Bertuletti, Marco Garofalo, Angelo Schiavone, Pasquale Davide Atienza, David Benini, Luca |
| author_facet | Cammarata, Danilo Perotti, Matteo Bertuletti, Marco Garofalo, Angelo Schiavone, Pasquale Davide Atienza, David Benini, Luca |
| contents | The rapid growth of AI-based Internet-of-Things applications increased the demand for high-performance edge processing engines on a low-power budget and tight area constraints. As a consequence, vector processor architectures, traditionally designed for high-performance computing (HPC), made their way into edge devices, promising high utilization of floating-point units (FPUs) and low power consumption. However, vector processors can only exploit a single dimension of parallelism, leading to expensive accesses to the vector register file (VRF) when performing matrix computations, which are pervasive in AI workloads. To overcome these limitations while guaranteeing programmability, many researchers and companies are developing dedicated instructions for a more efficient matrix multiplication (MatMul) execution. In this context, we propose Quadrilatero, an open-source RISC-V programmable systolic array coprocessor for low-power edge applications that implements a streamlined matrix ISA extension. We evaluate the post-synthesis power, performance, and area (PPA) metrics of Quadrilatero in a mature 65-nm technology node, showing that it requires only 0.65 mm^2 and that it can reach up to 99.4% of FPU utilization. Compared to a state-of-the-art open-source RISC-V vector processor and a hybrid vector-matrix processor optimized for embedded applications, Quadrilatero improves area efficiency and energy efficiency by up to 77% and 15%, respectively. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2504_07565 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications Cammarata, Danilo Perotti, Matteo Bertuletti, Marco Garofalo, Angelo Schiavone, Pasquale Davide Atienza, David Benini, Luca Hardware Architecture The rapid growth of AI-based Internet-of-Things applications increased the demand for high-performance edge processing engines on a low-power budget and tight area constraints. As a consequence, vector processor architectures, traditionally designed for high-performance computing (HPC), made their way into edge devices, promising high utilization of floating-point units (FPUs) and low power consumption. However, vector processors can only exploit a single dimension of parallelism, leading to expensive accesses to the vector register file (VRF) when performing matrix computations, which are pervasive in AI workloads. To overcome these limitations while guaranteeing programmability, many researchers and companies are developing dedicated instructions for a more efficient matrix multiplication (MatMul) execution. In this context, we propose Quadrilatero, an open-source RISC-V programmable systolic array coprocessor for low-power edge applications that implements a streamlined matrix ISA extension. We evaluate the post-synthesis power, performance, and area (PPA) metrics of Quadrilatero in a mature 65-nm technology node, showing that it requires only 0.65 mm^2 and that it can reach up to 99.4% of FPU utilization. Compared to a state-of-the-art open-source RISC-V vector processor and a hybrid vector-matrix processor optimized for embedded applications, Quadrilatero improves area efficiency and energy efficiency by up to 77% and 15%, respectively. |
| title | Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2504.07565 |