High-Level Synthesis using SDF-AP, Template Haskell, QuasiQuotes, and GADTs to Generate Circuits from Hierarchical Input Specification
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arXiv
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| Format: | Preprint |
| Publié: |
2025
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| _version_ | 1866909573834604544 |
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| author | Folmer, Hendrik |
| author_facet | Folmer, Hendrik |
| contents | FPGAs provide highly parallel and customizable hardware solutions but are traditionally programmed using low-level Hardware Description Languages (HDLs) like VHDL and Verilog. These languages have a low level of abstraction and require engineers to manage control and scheduling manually. High-Level Synthesis (HLS) tools attempt to lift this level of abstraction by translating C/C++ code into hardware descriptions, but their reliance on imperative paradigms leads to challenges in deriving parallelism due to pointer aliasing and sequential execution models.
Functional programming, with its inherent purity, immutability, and parallelism, presents a more natural abstraction for FPGA design. Existing functional hardware description tools such as Clash enable high-level circuit descriptions but lack automated scheduling and control mechanisms. Prior work by Folmer introduced a framework integrating SDF-AP graphs into Haskell for automatic hardware generation, but it lacked hierarchy and reusability.
This paper extends that framework by introducing hierarchical pattern specification, enabling structured composition and scalable parallelism. Key contributions include: (1) automatic hardware generation, where both data and control paths are derived from functional specifications with hierarchical patterns, (2) parameterized buffers using GADTs, eliminating the need for manual buffer definitions and facilitating component reuse, and (3) provision of a reference "golden model" that can be simulated in the integrated environment for validation.
The core focus of this paper is on methodology. But we also evaluate our approach against Vitis HLS, comparing both notation and resulting hardware architectures. Experimental results demonstrate that our method provides greater transparency in resource utilization and scheduling, often outperforming Vitis in both scheduling and predictability. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2504_07595 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | High-Level Synthesis using SDF-AP, Template Haskell, QuasiQuotes, and GADTs to Generate Circuits from Hierarchical Input Specification Folmer, Hendrik Hardware Architecture FPGAs provide highly parallel and customizable hardware solutions but are traditionally programmed using low-level Hardware Description Languages (HDLs) like VHDL and Verilog. These languages have a low level of abstraction and require engineers to manage control and scheduling manually. High-Level Synthesis (HLS) tools attempt to lift this level of abstraction by translating C/C++ code into hardware descriptions, but their reliance on imperative paradigms leads to challenges in deriving parallelism due to pointer aliasing and sequential execution models. Functional programming, with its inherent purity, immutability, and parallelism, presents a more natural abstraction for FPGA design. Existing functional hardware description tools such as Clash enable high-level circuit descriptions but lack automated scheduling and control mechanisms. Prior work by Folmer introduced a framework integrating SDF-AP graphs into Haskell for automatic hardware generation, but it lacked hierarchy and reusability. This paper extends that framework by introducing hierarchical pattern specification, enabling structured composition and scalable parallelism. Key contributions include: (1) automatic hardware generation, where both data and control paths are derived from functional specifications with hierarchical patterns, (2) parameterized buffers using GADTs, eliminating the need for manual buffer definitions and facilitating component reuse, and (3) provision of a reference "golden model" that can be simulated in the integrated environment for validation. The core focus of this paper is on methodology. But we also evaluate our approach against Vitis HLS, comparing both notation and resulting hardware architectures. Experimental results demonstrate that our method provides greater transparency in resource utilization and scheduling, often outperforming Vitis in both scheduling and predictability. |
| title | High-Level Synthesis using SDF-AP, Template Haskell, QuasiQuotes, and GADTs to Generate Circuits from Hierarchical Input Specification |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2504.07595 |