Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication
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arXiv
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| Format: | Preprint |
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2025
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| author | Nojehdeh, Mohammadreza Esmali Mokhtarnia, Hossein Rivera, Julian Pavon Quiroga, Narcis Rodas Bagué, Roger Figueras Reggiani, Enrico Moreto, Miquel Unsal, Osman Cristal, Adrian Ayguade, Eduard |
| author_facet | Nojehdeh, Mohammadreza Esmali Mokhtarnia, Hossein Rivera, Julian Pavon Quiroga, Narcis Rodas Bagué, Roger Figueras Reggiani, Enrico Moreto, Miquel Unsal, Osman Cristal, Adrian Ayguade, Eduard |
| contents | This study presents the Cartesian Accumulative Matrix Pipeline (CAMP) architecture, a novel approach designed to enhance matrix multiplication in Vector Architectures (VAs) and Single Instruction Multiple Data (SIMD) units. CAMP improves the processing efficiency of Quantized Neural Networks (QNNs). Matrix multiplication is a cornerstone of machine learning applications, and its quantized versions are increasingly popular for more efficient operations. Unfortunately, existing VAs and SIMD-support units struggle to efficiently handle these quantized formats. In this work, we propose CAMP, a simple yet effective architecture that leverages a hybrid multiplier. The CAMP architecture significantly advances the performance of vector architectures in handling quantized data, enabling more efficient execution of matrix multiplication across various platforms, specifically targeting the ARMv8 Scalable Vector Extension (SVE) and edge RISC-V SIMD-based architectures. In addition to increasing throughput, CAMP's architectural design also contributes to energy efficiency, making it an effective solution for low-power applications. Evaluations on a range of Large Language Models (LLMs) and Convolutional Neural Networks (CNNs) demonstrate that matrix multiplication operations using the proposed micro-architecture achieve up to 17$\times$ and 23$\times$ performance improvements compared to their respective baselines, the ARM A64FX core and a RISC-V-based edge System-on-Chip (SoC). Furthermore, synthesis and place-and-route (PnR) of the CAMP micro-architecture using Synopsys tools -- targeting ARM TSMC 7nm for A64FX and GlobalFoundries 22nm for the RISC-V SoC -- add only 1\% and 4\% area overhead, respectively, compared to the baseline designs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2504_08137 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication Nojehdeh, Mohammadreza Esmali Mokhtarnia, Hossein Rivera, Julian Pavon Quiroga, Narcis Rodas Bagué, Roger Figueras Reggiani, Enrico Moreto, Miquel Unsal, Osman Cristal, Adrian Ayguade, Eduard Hardware Architecture This study presents the Cartesian Accumulative Matrix Pipeline (CAMP) architecture, a novel approach designed to enhance matrix multiplication in Vector Architectures (VAs) and Single Instruction Multiple Data (SIMD) units. CAMP improves the processing efficiency of Quantized Neural Networks (QNNs). Matrix multiplication is a cornerstone of machine learning applications, and its quantized versions are increasingly popular for more efficient operations. Unfortunately, existing VAs and SIMD-support units struggle to efficiently handle these quantized formats. In this work, we propose CAMP, a simple yet effective architecture that leverages a hybrid multiplier. The CAMP architecture significantly advances the performance of vector architectures in handling quantized data, enabling more efficient execution of matrix multiplication across various platforms, specifically targeting the ARMv8 Scalable Vector Extension (SVE) and edge RISC-V SIMD-based architectures. In addition to increasing throughput, CAMP's architectural design also contributes to energy efficiency, making it an effective solution for low-power applications. Evaluations on a range of Large Language Models (LLMs) and Convolutional Neural Networks (CNNs) demonstrate that matrix multiplication operations using the proposed micro-architecture achieve up to 17$\times$ and 23$\times$ performance improvements compared to their respective baselines, the ARM A64FX core and a RISC-V-based edge System-on-Chip (SoC). Furthermore, synthesis and place-and-route (PnR) of the CAMP micro-architecture using Synopsys tools -- targeting ARM TSMC 7nm for A64FX and GlobalFoundries 22nm for the RISC-V SoC -- add only 1\% and 4\% area overhead, respectively, compared to the baseline designs. |
| title | Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2504.08137 |