Cover Image

Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Jiang, Limin, Shi, Yi, Shen, Yihao, Cao, Shan, Jiang, Zhiyuan, Zhou, Sheng
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)
by: Xu, Siyi, et al.
Published: (2025)

A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing
by: Jiang, Limin, et al.
Published: (2024)

RISC-V V Vector Extension (RVV) with reduced number of vector registers
by: Jacobs, Eino, et al.
Published: (2024)

VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
by: Wipfli, Max, et al.
Published: (2026)

Hypervisor Extension for a RISC-V Processor
by: Gauchola, Jaume, et al.
Published: (2024)

ARISE: Automating RISC-V Instruction Set Extension
by: Hager-Clukas, Andreas, et al.
Published: (2025)

Support Vector Machines Classification on Bendable RISC-V
by: Vergos, Polykarpos, et al.
Published: (2025)

Efficient Implementation of RISC-V Vector Permutation Instructions
by: Titopoulos, Vasileios, et al.
Published: (2025)

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency
by: Perotti, Matteo, et al.
Published: (2023)

ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
by: Petrolo, Vincenzo, et al.
Published: (2025)

Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor
by: Papadopoulos, Nikolaos-Charalampos, et al.
Published: (2024)

Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors
by: Titopoulos, Vasileios, et al.
Published: (2025)

Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors
by: Colagrande, Luca, et al.
Published: (2025)

Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension
by: Fragkoulis, George-Marios, et al.
Published: (2024)

RISC-V R-Extension: Advancing Efficiency with Rented-Pipeline for Edge DNN Processing
by: Kim, Won Hyeok, et al.
Published: (2024)

Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs
by: Titopoulos, Vasileios, et al.
Published: (2025)

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads
by: Perotti, Matteo, et al.
Published: (2024)

A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
by: Perotti, Matteo, et al.
Published: (2022)

IzhiRISC-V -- a RISC-V-based Processor with Custom ISA Extension for Spiking Neuron Networks Processing with Izhikevich Neurons
by: Szczerek, Wiktor J., et al.
Published: (2025)

Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
by: Lei, Jie, et al.
Published: (2026)

A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference
by: Wang, Chuanning, et al.
Published: (2024)

Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
by: Wang, Weiying, et al.
Published: (2026)

In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
by: Spagnolo, Tommaso, et al.
Published: (2026)

MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products
by: İslamoğlu, Gamze, et al.
Published: (2025)

SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions
by: Manoni, Simone, et al.
Published: (2025)

Web-Based Simulator of Superscalar RISC-V Processors
by: Jaros, Jiri, et al.
Published: (2024)

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication
by: Perotti, Matteo, et al.
Published: (2024)

SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference
by: Wang, Chuanning, et al.
Published: (2024)

Not All Faults Are Equal: Transient-Fault Sensitivity Characterization of an Open-Source RISC-V Vector Cluster
by: Cai, Maoyuan, et al.
Published: (2026)

AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
by: Purayil, Navaneeth Kunhi, et al.
Published: (2025)

MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI
by: M, Ajay Kumar, et al.
Published: (2025)

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
by: Giorgi, Roberto, et al.
Published: (2025)

Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor
by: Kirschner, Maximilian, et al.
Published: (2024)

Wildcat: Educational RISC-V Microprocessors
by: Schoeberl, Martin
Published: (2025)

Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
by: Huo, Juncheng, et al.
Published: (2025)

CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device
by: and, Yan-Cheng Guo, et al.
Published: (2025)

e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
by: Machetti, Simone, et al.
Published: (2025)

Runtime Energy Monitoring for RISC-V Soft-Cores
by: Scionti, Alberto, et al.
Published: (2025)

Optimizing Energy Efficiency in Subthreshold RISC-V Cores
by: Djupdal, Asbjørn, et al.
Published: (2025)

MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores
by: Bertaccini, Luca, et al.
Published: (2022)