A Unified Hardware Accelerator for Fast Fourier Transform and Number Theoretic Transform

Fuente: arXiv

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Bibliographic Details
Main Authors:	Shrivastava, Rishabh, Ratnala, Chaitanya Prasad, Puli, Durga Manasa, Banerjee, Utsav
Format:	Preprint
Published:	2025
Subjects:	Cryptography and Security Signal Processing
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2504.11124