Guardado en:
| Autores principales: | Lu, Shao-Chien, Yeh, Chen-Chen, Cho, Hui-Lin, Lin, Yu-Cheng, Lin, Rung-Bin |
|---|---|
| Formato: | Preprint |
| Publicado: |
2025
|
| Materias: | |
| Acceso en línea: | https://arxiv.org/abs/2504.12076 |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares
Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
por: Zhu, Jingchen, et al.
Publicado: (2024)
por: Zhu, Jingchen, et al.
Publicado: (2024)
RLPlanner: Reinforcement Learning based Floorplanning for Chiplets with Fast Thermal Analysis
por: Duan, Yuanyuan, et al.
Publicado: (2023)
por: Duan, Yuanyuan, et al.
Publicado: (2023)
Hecaton: Training Large Language Models with Scalable Chiplet Systems
por: Huang, Zongle, et al.
Publicado: (2024)
por: Huang, Zongle, et al.
Publicado: (2024)
A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration
por: Huang, Wei-Hsing, et al.
Publicado: (2025)
por: Huang, Wei-Hsing, et al.
Publicado: (2025)
WISP: Image Segmentation-Based Whitespace Diagnosis for Optimal Rectilinear Floorplanning
por: Zhao, Xiaotian, et al.
Publicado: (2025)
por: Zhao, Xiaotian, et al.
Publicado: (2025)
Floorplanning with I/O assignment via feasibility-seeking and superiorization methods
por: Yu, Shan, et al.
Publicado: (2024)
por: Yu, Shan, et al.
Publicado: (2024)
Enhancing Finite State Machine Design Automation with Large Language Models and Prompt Engineering Techniques
por: Lin, Qun-Kai, et al.
Publicado: (2025)
por: Lin, Qun-Kai, et al.
Publicado: (2025)
HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
por: Meng, Chang-Chih, et al.
Publicado: (2026)
por: Meng, Chang-Chih, et al.
Publicado: (2026)
BBAL: A Bidirectional Block Floating Point-Based Quantisation Accelerator for Large Language Models
por: Han, Xiaomeng, et al.
Publicado: (2025)
por: Han, Xiaomeng, et al.
Publicado: (2025)
LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization
por: Di, Zhixiong, et al.
Publicado: (2023)
por: Di, Zhixiong, et al.
Publicado: (2023)
3D-Carbon: An Analytical Carbon Modeling Tool for 3D and 2.5D Integrated Circuits
por: Zhao, Yujie, et al.
Publicado: (2023)
por: Zhao, Yujie, et al.
Publicado: (2023)
ACALSim: A Scalable Parallel Simulation Framework for High-Performance System Design Space Exploration
por: Lin, Wei-Fen, et al.
Publicado: (2026)
por: Lin, Wei-Fen, et al.
Publicado: (2026)
Managing Hybrid Solid-State Drives Using Large Language Models
por: Wei, Qian, et al.
Publicado: (2025)
por: Wei, Qian, et al.
Publicado: (2025)
GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models
por: Fu, Yonggan, et al.
Publicado: (2023)
por: Fu, Yonggan, et al.
Publicado: (2023)
Lumina: Real-Time Mobile Neural Rendering by Exploiting Computational Redundancy
por: Feng, Yu, et al.
Publicado: (2025)
por: Feng, Yu, et al.
Publicado: (2025)
Core Placement Optimization of Many-core Brain-Inspired Near-Storage Systems for Spiking Neural Network Training
por: Zhu, Xueke, et al.
Publicado: (2024)
por: Zhu, Xueke, et al.
Publicado: (2024)
Scaling Routers with In-Package Optics and High-Bandwidth Memories
por: Keslassy, Isaac, et al.
Publicado: (2026)
por: Keslassy, Isaac, et al.
Publicado: (2026)
Global and Local Attention-based Inception U-Net for Static IR Drop Prediction
por: Chen, Yilu, et al.
Publicado: (2024)
por: Chen, Yilu, et al.
Publicado: (2024)
Assessing Large Language Models in Generating RTL Design Specifications
por: Huang, Hung-Ming, et al.
Publicado: (2025)
por: Huang, Hung-Ming, et al.
Publicado: (2025)
GSIM: Accelerating RTL Simulation for Large-Scale Designs
por: Chen, Lu, et al.
Publicado: (2025)
por: Chen, Lu, et al.
Publicado: (2025)
RulePlanner: All-in-One Reinforcement Learner for Unifying Design Rules in 3D Floorplanning
por: Zhong, Ruizhe, et al.
Publicado: (2026)
por: Zhong, Ruizhe, et al.
Publicado: (2026)
Computing-In-Memory Aware Model Adaption For Edge Devices
por: Lin, Ming-Han, et al.
Publicado: (2025)
por: Lin, Ming-Han, et al.
Publicado: (2025)
HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip
por: Tsai, Pei-Huan, et al.
Publicado: (2026)
por: Tsai, Pei-Huan, et al.
Publicado: (2026)
Hummingbird: A Smaller and Faster Large Language Model Accelerator on Embedded FPGA
por: Li, Jindong, et al.
Publicado: (2025)
por: Li, Jindong, et al.
Publicado: (2025)
LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models
por: Fang, Zhigang, et al.
Publicado: (2025)
por: Fang, Zhigang, et al.
Publicado: (2025)
SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
por: He, Zicheng, et al.
Publicado: (2026)
por: He, Zicheng, et al.
Publicado: (2026)
Large Processor Chip Model
por: Chang, Kaiyan, et al.
Publicado: (2025)
por: Chang, Kaiyan, et al.
Publicado: (2025)
SimulatorCoder: DNN Accelerator Simulator Code Generation and Optimization via Large Language Models
por: Xia, Yuhuan, et al.
Publicado: (2026)
por: Xia, Yuhuan, et al.
Publicado: (2026)
VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
por: Zhao, Zhuorui, et al.
Publicado: (2025)
por: Zhao, Zhuorui, et al.
Publicado: (2025)
Energy-Oriented Computing Architecture Simulator for SNN Training
por: Ma, Yunhao, et al.
Publicado: (2025)
por: Ma, Yunhao, et al.
Publicado: (2025)
MX+: Pushing the Limits of Microscaling Formats for Efficient Large Language Model Serving
por: Lee, Jungi, et al.
Publicado: (2025)
por: Lee, Jungi, et al.
Publicado: (2025)
PASCAL: A Phase-Aware Scheduling Algorithm for Serving Reasoning-based Large Language Models
por: Cho, Eunyeong, et al.
Publicado: (2026)
por: Cho, Eunyeong, et al.
Publicado: (2026)
An Extended Study of Gear-Ratio-Aware Standard Cell Layout Generation for DTCO Exploration
por: Cheng, Chung-Kuan, et al.
Publicado: (2026)
por: Cheng, Chung-Kuan, et al.
Publicado: (2026)
TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines
por: Wang, Jiayi, et al.
Publicado: (2026)
por: Wang, Jiayi, et al.
Publicado: (2026)
VitaLLM: A Versatile, Ultra-Compact Ternary LLM Accelerator with Dependency-Aware Scheduling
por: Lin, Zi-Wei, et al.
Publicado: (2026)
por: Lin, Zi-Wei, et al.
Publicado: (2026)
Polaris: Multi-Fidelity Design Space Exploration of Deep Learning Accelerators
por: Sakhuja, Chirag, et al.
Publicado: (2024)
por: Sakhuja, Chirag, et al.
Publicado: (2024)
Voxel-CIM: An Efficient Compute-in-Memory Accelerator for Voxel-based Point Cloud Neural Networks
por: Lin, Xipeng, et al.
Publicado: (2024)
por: Lin, Xipeng, et al.
Publicado: (2024)
VitaLLM: A Versatile and Tiny Accelerator for Mixed-Precision LLM Inference on Edge Devices
por: Lin, Zi-Wei, et al.
Publicado: (2026)
por: Lin, Zi-Wei, et al.
Publicado: (2026)
ITERA-LLM: Boosting Sub-8-Bit Large Language Model Inference via Iterative Tensor Decomposition
por: Zheng, Keran, et al.
Publicado: (2025)
por: Zheng, Keran, et al.
Publicado: (2025)
Multimodal Chip Physical Design Engineer Assistant
por: Tsai, Yun-Da, et al.
Publicado: (2025)
por: Tsai, Yun-Da, et al.
Publicado: (2025)
Ejemplares similares
-
Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
por: Zhu, Jingchen, et al.
Publicado: (2024) -
RLPlanner: Reinforcement Learning based Floorplanning for Chiplets with Fast Thermal Analysis
por: Duan, Yuanyuan, et al.
Publicado: (2023) -
Hecaton: Training Large Language Models with Scalable Chiplet Systems
por: Huang, Zongle, et al.
Publicado: (2024) -
A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration
por: Huang, Wei-Hsing, et al.
Publicado: (2025) -
WISP: Image Segmentation-Based Whitespace Diagnosis for Optimal Rectilinear Floorplanning
por: Zhao, Xiaotian, et al.
Publicado: (2025)