A CMOS Probabilistic Computing Chip With In-situ hardware Aware Learning
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866910922370449408 |
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| author | Jhonsa, Jinesh Whitehead, William McCarthy, David Chowdhury, Shuvro Camsari, Kerem Theogarajan, Luke |
| author_facet | Jhonsa, Jinesh Whitehead, William McCarthy, David Chowdhury, Shuvro Camsari, Kerem Theogarajan, Luke |
| contents | This paper demonstrates a probabilistic bit physics inspired solver with 440 spins configured in a Chimera graph, occupying an area of 0.44 mm^2. Area efficiency is maximized through a current-mode implementation of the neuron update circuit, standard cell design for analog blocks pitch-matched to digital blocks, and a shared power supply for both digital and analog components. Process variation related mismatches introduced by this approach are effectively mitigated using a hardware aware contrastive divergence algorithm during training. We validate the chip's ability to perform probabilistic computing tasks such as modeling logic gates and full adders, as well as optimization tasks such as MaxCut, demonstrating its potential for AI and machine learning applications. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2504_14070 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A CMOS Probabilistic Computing Chip With In-situ hardware Aware Learning Jhonsa, Jinesh Whitehead, William McCarthy, David Chowdhury, Shuvro Camsari, Kerem Theogarajan, Luke Hardware Architecture Artificial Intelligence This paper demonstrates a probabilistic bit physics inspired solver with 440 spins configured in a Chimera graph, occupying an area of 0.44 mm^2. Area efficiency is maximized through a current-mode implementation of the neuron update circuit, standard cell design for analog blocks pitch-matched to digital blocks, and a shared power supply for both digital and analog components. Process variation related mismatches introduced by this approach are effectively mitigated using a hardware aware contrastive divergence algorithm during training. We validate the chip's ability to perform probabilistic computing tasks such as modeling logic gates and full adders, as well as optimization tasks such as MaxCut, demonstrating its potential for AI and machine learning applications. |
| title | A CMOS Probabilistic Computing Chip With In-situ hardware Aware Learning |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2504.14070 |