TeLLMe: An Energy-Efficient Ternary LLM Accelerator for Prefilling and Decoding on Edge FPGAs
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arXiv
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| Main Authors: | Qiao, Ye, Chen, Zhiheng, Zhang, Yifan, Wang, Yian, Huang, Sitao |
|---|---|
| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | |
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