ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy

Fuente: arXiv

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Bibliographic Details
Main Authors:	Tang, Jiaping, Mu, Jianan, Liu, Silin, Liu, Zizhen, Gu, Feng, Zhang, Xinyu, Wang, Leyan, Liang, Shenwen, Ye, Jing, Li, Huawei, Li, Xiaowei
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2504.16473