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Memory-efficient Sketch Acceleration for Handling Large Network Flows on FPGAs

Fuente: arXiv

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Détails bibliographiques
Auteurs principaux:	Han, Zhaoyang, Qian, Yicheng, Zink, Michael, Leeser, Miriam
Format:	Preprint
Publié:	2025
Sujets:	Hardware Architecture Networking and Internet Architecture
Accès en ligne:	Acceder al recurso
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

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