ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866908339937476608 |
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| author | Wang, Bowei Gao, Jiaran Feng, Yelai Chen, Renzhi Li, Shanshan Wang, Lei |
| author_facet | Wang, Bowei Gao, Jiaran Feng, Yelai Chen, Renzhi Li, Shanshan Wang, Lei |
| contents | The growing demand for Domain-Specific Architecture (DSA) has driven the development of Agile Hardware Development Methodology (AHDM). Hardware Construction Language (HCL) like Chisel offers high-level abstraction features, making it an ideal language for HCL-Based AHDM. While Large Language Models (LLMs) excel in code generation tasks, they still face challenges with Chisel generation, particularly regarding syntax correctness and design variability. Recent reasoning models have significantly enhanced code generation capabilities through test-time scaling techniques. However, we found that reasoning models without domain adaptation cannot bring substantial benefits to Chisel code generation tasks. This paper presents ChiseLLM, a solution comprising data processing and transformation, prompt-guided reasoning trace synthesis, and domain-adapted model training. We constructed high-quality datasets from public RTL code resources and guided the model to adopt structured thinking patterns through prompt enhancement methods. Experiments demonstrate that our ChiseLLM-7B and ChiseLLM-32B models improved syntax correctness by 18.85% and 26.32% respectively over base models, while increasing variability design ability by 47.58% compared to baseline reasoning models. Our datasets and models are publicly available, providing high-performance, cost-effective models for HCL-Based AHDM, and offering an effective baseline for future research. Github repository: https://github.com/observerw/ChiseLLM |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2504_19144 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development Wang, Bowei Gao, Jiaran Feng, Yelai Chen, Renzhi Li, Shanshan Wang, Lei Artificial Intelligence Hardware Architecture Software Engineering The growing demand for Domain-Specific Architecture (DSA) has driven the development of Agile Hardware Development Methodology (AHDM). Hardware Construction Language (HCL) like Chisel offers high-level abstraction features, making it an ideal language for HCL-Based AHDM. While Large Language Models (LLMs) excel in code generation tasks, they still face challenges with Chisel generation, particularly regarding syntax correctness and design variability. Recent reasoning models have significantly enhanced code generation capabilities through test-time scaling techniques. However, we found that reasoning models without domain adaptation cannot bring substantial benefits to Chisel code generation tasks. This paper presents ChiseLLM, a solution comprising data processing and transformation, prompt-guided reasoning trace synthesis, and domain-adapted model training. We constructed high-quality datasets from public RTL code resources and guided the model to adopt structured thinking patterns through prompt enhancement methods. Experiments demonstrate that our ChiseLLM-7B and ChiseLLM-32B models improved syntax correctness by 18.85% and 26.32% respectively over base models, while increasing variability design ability by 47.58% compared to baseline reasoning models. Our datasets and models are publicly available, providing high-performance, cost-effective models for HCL-Based AHDM, and offering an effective baseline for future research. Github repository: https://github.com/observerw/ChiseLLM |
| title | ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development |
| topic | Artificial Intelligence Hardware Architecture Software Engineering |
| url | https://arxiv.org/abs/2504.19144 |