Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs
Fuente:
arXiv
Saved in:
| Main Authors: | Sabih, Muhammad, Karim, Abrarul, Wittmann, Jakob, Hannig, Frank, Teich, Jürgen |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Loop Control Management in Tightly Coupled Processor Arrays (TCPAs)
by: Walter, Dominik, et al.
Published: (2026)
by: Walter, Dominik, et al.
Published: (2026)
Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design
by: Liao, Yuchao, et al.
Published: (2026)
by: Liao, Yuchao, et al.
Published: (2026)
Co-Design of CNN Accelerators for TinyML using Approximate Matrix Decomposition
by: Morales, José Juan Hernández, et al.
Published: (2026)
by: Morales, José Juan Hernández, et al.
Published: (2026)
EdgeCIM: A Hardware-Software Co-Design for CIM-Based Acceleration of Small Language Models
by: Bazzi, Jinane, et al.
Published: (2026)
by: Bazzi, Jinane, et al.
Published: (2026)
RISC-V R-Extension: Advancing Efficiency with Rented-Pipeline for Edge DNN Processing
by: Kim, Won Hyeok, et al.
Published: (2024)
by: Kim, Won Hyeok, et al.
Published: (2024)
Sparsity-Aware Hardware-Software Co-Design of Spiking Neural Networks: An Overview
by: Aliyev, Ilkin, et al.
Published: (2024)
by: Aliyev, Ilkin, et al.
Published: (2024)
Chiplet-Based RISC-V SoC with Modular AI Acceleration
by: Bharadwaj, Suhas Suresh, et al.
Published: (2025)
by: Bharadwaj, Suhas Suresh, et al.
Published: (2025)
Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE
by: Ahmad, Adeel, et al.
Published: (2025)
by: Ahmad, Adeel, et al.
Published: (2025)
Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimization
by: Krestinskaya, Olga, et al.
Published: (2024)
by: Krestinskaya, Olga, et al.
Published: (2024)
Beyond Moore's Law: Harnessing the Redshift of Generative AI with Effective Hardware-Software Co-Design
by: Yazdanbakhsh, Amir
Published: (2025)
by: Yazdanbakhsh, Amir
Published: (2025)
Symbolic Polyhedral-Based Energy Analysis for Nested Loop Programs
by: Nirmala, Avinash Mahesh, et al.
Published: (2026)
by: Nirmala, Avinash Mahesh, et al.
Published: (2026)
Assessing Tenstorrent's RISC-V MatMul Acceleration Capabilities
by: Cavagna, Hiari Pizzini, et al.
Published: (2025)
by: Cavagna, Hiari Pizzini, et al.
Published: (2025)
KWT-Tiny: RISC-V Accelerated, Embedded Keyword Spotting Transformer
by: Al-Qawlaq, Aness, et al.
Published: (2024)
by: Al-Qawlaq, Aness, et al.
Published: (2024)
SWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs
by: Bai, Zhenyu, et al.
Published: (2024)
by: Bai, Zhenyu, et al.
Published: (2024)
SoftmAP: Software-Hardware Co-design for Integer-Only Softmax on Associative Processors
by: Rakka, Mariam, et al.
Published: (2024)
by: Rakka, Mariam, et al.
Published: (2024)
Comprehensive Design Space Exploration for Tensorized Neural Network Hardware Accelerators
by: Zhang, Jinsong, et al.
Published: (2025)
by: Zhang, Jinsong, et al.
Published: (2025)
Hardware-Software Co-Design for Event-Driven SNN Deployment on Low-Cost Neuromorphic FPGAs
by: Lee, Jiwoon, et al.
Published: (2026)
by: Lee, Jiwoon, et al.
Published: (2026)
BitParticle: Partializing Sparse Dual-Factors to Build Quasi-Synchronizing MAC Arrays for Energy-efficient DNNs
by: Qiaoyuan, Feilong, et al.
Published: (2025)
by: Qiaoyuan, Feilong, et al.
Published: (2025)
GRAU: Generic Reconfigurable Activation Unit Design for Neural Network Hardware Accelerators
by: Liu, Yuhao, et al.
Published: (2026)
by: Liu, Yuhao, et al.
Published: (2026)
Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU
by: The Verkor Team, et al.
Published: (2026)
by: The Verkor Team, et al.
Published: (2026)
APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
by: Tan, Yonghao, et al.
Published: (2025)
by: Tan, Yonghao, et al.
Published: (2025)
OpenGeMM: A High-Utilization GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling
by: Yi, Xiaoling, et al.
Published: (2024)
by: Yi, Xiaoling, et al.
Published: (2024)
GenAI-Driven Approach to RISC-V Supply Chain Exploration
by: Petrovic, Nenad, et al.
Published: (2026)
by: Petrovic, Nenad, et al.
Published: (2026)
SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions
by: Manoni, Simone, et al.
Published: (2025)
by: Manoni, Simone, et al.
Published: (2025)
A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs
by: Dang, Peng, et al.
Published: (2024)
by: Dang, Peng, et al.
Published: (2024)
Full-stack evaluation of Machine Learning inference workloads for RISC-V systems
by: Bhattacharjee, Debjyoti, et al.
Published: (2024)
by: Bhattacharjee, Debjyoti, et al.
Published: (2024)
A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
by: Jaswal, Pragun, et al.
Published: (2026)
by: Jaswal, Pragun, et al.
Published: (2026)
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation
by: Valente, Luca, et al.
Published: (2024)
by: Valente, Luca, et al.
Published: (2024)
Hardware Acceleration of LLMs: A comprehensive survey and comparison
by: Koilia, Nikoletta, et al.
Published: (2024)
by: Koilia, Nikoletta, et al.
Published: (2024)
AccLLM: Accelerating Long-Context LLM Inference Via Algorithm-Hardware Co-Design
by: Liang, Yanbiao, et al.
Published: (2025)
by: Liang, Yanbiao, et al.
Published: (2025)
HiAER-Spike Software-Hardware Reconfigurable Platform for Event-Driven Neuromorphic Computing at Scale
by: Frank, Gwenevere, et al.
Published: (2026)
by: Frank, Gwenevere, et al.
Published: (2026)
Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing
by: Li, Qiong, et al.
Published: (2025)
by: Li, Qiong, et al.
Published: (2025)
SpikeX: Exploring Accelerator Architecture and Network-Hardware Co-Optimization for Sparse Spiking Neural Networks
by: Xu, Boxun, et al.
Published: (2025)
by: Xu, Boxun, et al.
Published: (2025)
RISC-V V Vector Extension (RVV) with reduced number of vector registers
by: Jacobs, Eino, et al.
Published: (2024)
by: Jacobs, Eino, et al.
Published: (2024)
A Configurable and Efficient Memory Hierarchy for Neural Network Hardware Accelerator
by: Bause, Oliver, et al.
Published: (2024)
by: Bause, Oliver, et al.
Published: (2024)
Resource Utilization of Differentiable Logic Gate Networks Deployed on FPGAs
by: Wormald, Stephen, et al.
Published: (2026)
by: Wormald, Stephen, et al.
Published: (2026)
Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operations
by: Armeniakos, Giorgos, et al.
Published: (2024)
by: Armeniakos, Giorgos, et al.
Published: (2024)
FAMOUS: Flexible Accelerator for the Attention Mechanism of Transformer on UltraScale+ FPGAs
by: Kabir, Ehsan, et al.
Published: (2024)
by: Kabir, Ehsan, et al.
Published: (2024)
MC$^2$A: Enabling Algorithm-Hardware Co-Design for Efficient Markov Chain Monte Carlo Acceleration
by: Zhao, Shirui, et al.
Published: (2025)
by: Zhao, Shirui, et al.
Published: (2025)
Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU
by: Pu, Huanzhi, et al.
Published: (2025)
by: Pu, Huanzhi, et al.
Published: (2025)
Similar Items
-
Loop Control Management in Tightly Coupled Processor Arrays (TCPAs)
by: Walter, Dominik, et al.
Published: (2026) -
Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design
by: Liao, Yuchao, et al.
Published: (2026) -
Co-Design of CNN Accelerators for TinyML using Approximate Matrix Decomposition
by: Morales, José Juan Hernández, et al.
Published: (2026) -
EdgeCIM: A Hardware-Software Co-Design for CIM-Based Acceleration of Small Language Models
by: Bazzi, Jinane, et al.
Published: (2026) -
RISC-V R-Extension: Advancing Efficiency with Rented-Pipeline for Edge DNN Processing
by: Kim, Won Hyeok, et al.
Published: (2024)