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| Auteurs principaux: | , , , , , , , , , |
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| Format: | Preprint |
| Publié: |
2025
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| Sujets: | |
| Accès en ligne: | https://arxiv.org/abs/2504.20653 |
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| _version_ | 1866908521781526528 |
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| author | Zuo, Jian Liu, Junzhe Wang, Xianyong Liu, Yicheng Goli, Navya Xu, Tong Zhang, Hao Tida, Umamaheswara Rao Jia, Zhenge Zhao, Mengying |
| author_facet | Zuo, Jian Liu, Junzhe Wang, Xianyong Liu, Yicheng Goli, Navya Xu, Tong Zhang, Hao Tida, Umamaheswara Rao Jia, Zhenge Zhao, Mengying |
| contents | Recent advances have demonstrated the promising capabilities of large language models (LLMs) in generating register-transfer level (RTL) code, such as Verilog. However, existing LLM-based frameworks still face significant challenges in accurately handling the complexity of real-world RTL designs, particularly those that are large-scale and involve multi-level module instantiations. To address this issue, we present ComplexVCoder, an open-source LLM-driven framework that enhances both the generation quality and efficiency of complex Verilog code. Specifically, we introduce a two-stage generation mechanism, which leverages an intermediate representation to enable a more accurate and structured transition from natural language descriptions to intricate Verilog designs. In addition, we introduce a rule-based alignment method and a domain-specific retrieval-augmented generation (RAG) to further improve the correctness of the synthesized code by incorporating relevant design knowledge during generation. To evaluate our approach, we construct a comprehensive dataset comprising 55 complex Verilog designs derived from real-world implementations. We also release an open-source benchmark suite for systematically assessing the quality of auto-generated RTL code together with the ComplexVCoder framework. Experimental results show that ComplexVCoder outperforms SOTA frameworks such as CodeV and RTLCoder by 14.6% and 22.2%, respectively, in terms of function correctness on complex Verilog benchmarks. Furthermore, ComplexVcoder achieves comparable generation performances in terms of functionality correctness using a lightweight 32B model (Qwen2.5), rivaling larger-scale models such as GPT-3.5 and DeepSeek-V3. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2504_20653 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | ComplexVCoder: An LLM-Driven Framework for Systematic Generation of Complex Verilog Code Zuo, Jian Liu, Junzhe Wang, Xianyong Liu, Yicheng Goli, Navya Xu, Tong Zhang, Hao Tida, Umamaheswara Rao Jia, Zhenge Zhao, Mengying Software Engineering Systems and Control Recent advances have demonstrated the promising capabilities of large language models (LLMs) in generating register-transfer level (RTL) code, such as Verilog. However, existing LLM-based frameworks still face significant challenges in accurately handling the complexity of real-world RTL designs, particularly those that are large-scale and involve multi-level module instantiations. To address this issue, we present ComplexVCoder, an open-source LLM-driven framework that enhances both the generation quality and efficiency of complex Verilog code. Specifically, we introduce a two-stage generation mechanism, which leverages an intermediate representation to enable a more accurate and structured transition from natural language descriptions to intricate Verilog designs. In addition, we introduce a rule-based alignment method and a domain-specific retrieval-augmented generation (RAG) to further improve the correctness of the synthesized code by incorporating relevant design knowledge during generation. To evaluate our approach, we construct a comprehensive dataset comprising 55 complex Verilog designs derived from real-world implementations. We also release an open-source benchmark suite for systematically assessing the quality of auto-generated RTL code together with the ComplexVCoder framework. Experimental results show that ComplexVCoder outperforms SOTA frameworks such as CodeV and RTLCoder by 14.6% and 22.2%, respectively, in terms of function correctness on complex Verilog benchmarks. Furthermore, ComplexVcoder achieves comparable generation performances in terms of functionality correctness using a lightweight 32B model (Qwen2.5), rivaling larger-scale models such as GPT-3.5 and DeepSeek-V3. |
| title | ComplexVCoder: An LLM-Driven Framework for Systematic Generation of Complex Verilog Code |
| topic | Software Engineering Systems and Control |
| url | https://arxiv.org/abs/2504.20653 |