Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field

Fuente: arXiv

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Bibliographic Details
Main Authors:	Hossain, Md Rownak, Rahman, Md Sazedur, Zaman, Kh Shahriya, Fezzani, Walid El, Bhuiyan, Mohammad Arif Sobhan, Kang, Chia Chao, Yew, Teh Jia, Miraz, Mahdi H.
Format:	Preprint
Published:	2025
Subjects:	Cryptography and Security Networking and Internet Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2504.21342