ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA
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arXiv
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| Format: | Preprint |
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2025
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| author | Shi, Zhengyuan Li, Zeju Ma, Chengyu Zhou, Yunhao Zheng, Ziyang Liu, Jiawei Pan, Hongyang Zhou, Lingfeng Li, Kezhi Zhu, Jiaying Yan, Lingwei He, Zhiqiang Xue, Chenhao Jiang, Wentao Yang, Fan Sun, Guangyu Yang, Xiaoyan Chen, Gang Shi, Chuan Chu, Zhufei Yang, Jun Xu, Qiang |
| author_facet | Shi, Zhengyuan Li, Zeju Ma, Chengyu Zhou, Yunhao Zheng, Ziyang Liu, Jiawei Pan, Hongyang Zhou, Lingfeng Li, Kezhi Zhu, Jiaying Yan, Lingwei He, Zhiqiang Xue, Chenhao Jiang, Wentao Yang, Fan Sun, Guangyu Yang, Xiaoyan Chen, Gang Shi, Chuan Chu, Zhufei Yang, Jun Xu, Qiang |
| contents | We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post-mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development. We demonstrate ForgeEDA's utility by benchmarking state-of-the-art EDA algorithms on critical tasks such as Power, Performance, and Area (PPA) optimization, highlighting its ability to expose performance gaps and drive advancements. Additionally, ForgeEDA's scale and diversity facilitate the training of AI models for EDA tasks, demonstrating its potential to improve model performance and generalization. By addressing limitations in existing datasets, ForgeEDA aims to catalyze breakthroughs in modern IC design and support the next generation of innovations in EDA. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_02016 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA Shi, Zhengyuan Li, Zeju Ma, Chengyu Zhou, Yunhao Zheng, Ziyang Liu, Jiawei Pan, Hongyang Zhou, Lingfeng Li, Kezhi Zhu, Jiaying Yan, Lingwei He, Zhiqiang Xue, Chenhao Jiang, Wentao Yang, Fan Sun, Guangyu Yang, Xiaoyan Chen, Gang Shi, Chuan Chu, Zhufei Yang, Jun Xu, Qiang Hardware Architecture We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post-mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development. We demonstrate ForgeEDA's utility by benchmarking state-of-the-art EDA algorithms on critical tasks such as Power, Performance, and Area (PPA) optimization, highlighting its ability to expose performance gaps and drive advancements. Additionally, ForgeEDA's scale and diversity facilitate the training of AI models for EDA tasks, demonstrating its potential to improve model performance and generalization. By addressing limitations in existing datasets, ForgeEDA aims to catalyze breakthroughs in modern IC design and support the next generation of innovations in EDA. |
| title | ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2505.02016 |