Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU
Fuente:
arXiv
Saved in:
| Main Authors: | Pu, Huanzhi, Ravi, Rishabh, Jeong, Shinnung, Subramanya, Udit, Chung, Euijun, Zhao, Jisheng, Ahn, Chihyo, Kim, Hyesoon |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
CuLifter: Lifting GPU Binaries to Typed IR
by: Zhao, Jisheng, et al.
Published: (2026)
by: Zhao, Jisheng, et al.
Published: (2026)
Inside VOLT: Designing an Open-Source GPU Compiler
by: Jeong, Shinnung, et al.
Published: (2025)
by: Jeong, Shinnung, et al.
Published: (2025)
Towards Performance-Aware Allocation for Accelerated Machine Learning on GPU-SSD Systems
by: Gundawar, Ayush, et al.
Published: (2024)
by: Gundawar, Ayush, et al.
Published: (2024)
Characterizing CPU-Induced Slowdowns in Multi-GPU LLM Inference
by: Chung, Euijun, et al.
Published: (2026)
by: Chung, Euijun, et al.
Published: (2026)
Vorion: A RISC-V GPU with Hardware-Accelerated 3D Gaussian Rendering and Training
by: Wang, Yipeng, et al.
Published: (2025)
by: Wang, Yipeng, et al.
Published: (2025)
A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems
by: Bonet, Marc Solé i, et al.
Published: (2025)
by: Bonet, Marc Solé i, et al.
Published: (2025)
Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects
by: Ramsauer, Ralf, et al.
Published: (2022)
by: Ramsauer, Ralf, et al.
Published: (2022)
Multiport Support for Vortex OpenGPU Memory Hierarchy
by: Shin, Injae, et al.
Published: (2025)
by: Shin, Injae, et al.
Published: (2025)
Efficient Implementation of RISC-V Vector Permutation Instructions
by: Titopoulos, Vasileios, et al.
Published: (2025)
by: Titopoulos, Vasileios, et al.
Published: (2025)
Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs
by: Sabih, Muhammad, et al.
Published: (2025)
by: Sabih, Muhammad, et al.
Published: (2025)
Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor
by: Papadopoulos, Nikolaos-Charalampos, et al.
Published: (2024)
by: Papadopoulos, Nikolaos-Charalampos, et al.
Published: (2024)
Hardware-Aware Neural Network Compilation with Learned Optimization: A RISC-V Accelerator Approach
by: Ganti, Ravindra, et al.
Published: (2025)
by: Ganti, Ravindra, et al.
Published: (2025)
e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
by: Machetti, Simone, et al.
Published: (2025)
by: Machetti, Simone, et al.
Published: (2025)
A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges
by: Zhong, Xinchao, et al.
Published: (2024)
by: Zhong, Xinchao, et al.
Published: (2024)
Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
by: Huo, Juncheng, et al.
Published: (2025)
by: Huo, Juncheng, et al.
Published: (2025)
Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension
by: Fragkoulis, George-Marios, et al.
Published: (2024)
by: Fragkoulis, George-Marios, et al.
Published: (2024)
NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI
by: Yang, Kaiyuan, et al.
Published: (2025)
by: Yang, Kaiyuan, et al.
Published: (2025)
Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware Implementation
by: Tran, Van Duy, et al.
Published: (2024)
by: Tran, Van Duy, et al.
Published: (2024)
Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
by: Vanoni, Axel, et al.
Published: (2026)
by: Vanoni, Axel, et al.
Published: (2026)
Functional Stability of Software-Hardware Neural Network Implementation The NeuroComp Project
by: Oleksii, Bychkov, et al.
Published: (2025)
by: Oleksii, Bychkov, et al.
Published: (2025)
Fused-Tiled Layers: Minimizing Data Movement on RISC-V SoCs with Software-Managed Caches
by: Jung, Victor J. B., et al.
Published: (2025)
by: Jung, Victor J. B., et al.
Published: (2025)
QED: Scalable Verification of Hardware Memory Consistency
by: Ravi, Gokulan, et al.
Published: (2024)
by: Ravi, Gokulan, et al.
Published: (2024)
A Power-Efficient Hardware Implementation of L-Mul
by: Chen, Ruiqi, et al.
Published: (2024)
by: Chen, Ruiqi, et al.
Published: (2024)
TLX: Hardware-Native, Evolvable MIMW GPU Compiler for Large-scale Production Environments
by: Guan, Yue, et al.
Published: (2026)
by: Guan, Yue, et al.
Published: (2026)
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores
by: Bertaccini, Luca, et al.
Published: (2022)
by: Bertaccini, Luca, et al.
Published: (2022)
WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
by: Giorgi, Roberto, et al.
Published: (2025)
by: Giorgi, Roberto, et al.
Published: (2025)
SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
by: Xuan, Wei, et al.
Published: (2025)
by: Xuan, Wei, et al.
Published: (2025)
GenDRAM:Hardware-Software Co-Design of General Platform in DRAM
by: Lu, Tsung-Han, et al.
Published: (2026)
by: Lu, Tsung-Han, et al.
Published: (2026)
Wildcat: Educational RISC-V Microprocessors
by: Schoeberl, Martin
Published: (2025)
by: Schoeberl, Martin
Published: (2025)
Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU
by: The Verkor Team, et al.
Published: (2026)
by: The Verkor Team, et al.
Published: (2026)
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
by: Ottaviano, Alessandro, et al.
Published: (2023)
by: Ottaviano, Alessandro, et al.
Published: (2023)
Optimal Software Pipelining and Warp Specialization for Tensor Core GPUs
by: Soi, Rupanshu, et al.
Published: (2025)
by: Soi, Rupanshu, et al.
Published: (2025)
C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?
by: Collini, Luca, et al.
Published: (2024)
by: Collini, Luca, et al.
Published: (2024)
METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators
by: Wang, Zhao, et al.
Published: (2021)
by: Wang, Zhao, et al.
Published: (2021)
Hardware-Software Co-Design for Accelerating Transformer Inference Leveraging Compute-in-Memory
by: Kim, Dong Eun, et al.
Published: (2025)
by: Kim, Dong Eun, et al.
Published: (2025)
NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering
by: Zhou, Zhe, et al.
Published: (2024)
by: Zhou, Zhe, et al.
Published: (2024)
Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
by: Darvishi, Mostafa
Published: (2025)
by: Darvishi, Mostafa
Published: (2025)
Hypervisor Extension for a RISC-V Processor
by: Gauchola, Jaume, et al.
Published: (2024)
by: Gauchola, Jaume, et al.
Published: (2024)
Implementation of Compute Intensive Algorithms on Software Configurable Processor
by: Ganesha, et al.
Published: (2025)
by: Ganesha, et al.
Published: (2025)
MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules
by: Raj, Ritik, et al.
Published: (2025)
by: Raj, Ritik, et al.
Published: (2025)
Similar Items
-
CuLifter: Lifting GPU Binaries to Typed IR
by: Zhao, Jisheng, et al.
Published: (2026) -
Inside VOLT: Designing an Open-Source GPU Compiler
by: Jeong, Shinnung, et al.
Published: (2025) -
Towards Performance-Aware Allocation for Accelerated Machine Learning on GPU-SSD Systems
by: Gundawar, Ayush, et al.
Published: (2024) -
Characterizing CPU-Induced Slowdowns in Multi-GPU LLM Inference
by: Chung, Euijun, et al.
Published: (2026) -
Vorion: A RISC-V GPU with Hardware-Accelerated 3D Gaussian Rendering and Training
by: Wang, Yipeng, et al.
Published: (2025)