Cover Image

APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Tan, Yonghao, Dong, Pingcheng, Wu, Yongkun, Liu, Yu, Liu, Xuejiao, Luo, Peng, Liu, Shih-Yang, Huang, Xijie, Zhang, Dong, Liang, Luhong, Cheng, Kwang-Ting
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Artificial Intelligence
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Genetic Quantization-Aware Approximation for Non-Linear Operations in Transformers
by: Dong, Pingcheng, et al.
Published: (2024)

31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding
by: Dong, Pingcheng, et al.
Published: (2026)

LLM-FP4: 4-Bit Floating-Point Quantized Transformers
by: Liu, Shih-yang, et al.
Published: (2023)

Expert Streaming: Accelerating Low-Batch MoE Inference via Multi-chiplet Architecture and Dynamic Expert Trajectory Scheduling
by: Ma, Songchen, et al.
Published: (2026)

CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design
by: Wan, Zishen, et al.
Published: (2025)

Hardware-Software Co-Design for Accelerating Transformer Inference Leveraging Compute-in-Memory
by: Kim, Dong Eun, et al.
Published: (2025)

CoQMoE: Co-Designed Quantization and Computation Orchestration for Mixture-of-Experts Vision Transformer on FPGA
by: Dong, Jiale, et al.
Published: (2025)

A 10.60 $μ$W 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection
by: Qin, Yifan, et al.
Published: (2024)

Harmonia: Algorithm-Hardware Co-Design for Memory- and Compute-Efficient BFP-based LLM Inference
by: Wang, Xinyu, et al.
Published: (2026)

Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning
by: Kanda, R., et al.
Published: (2026)

NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering
by: Zhou, Zhe, et al.
Published: (2024)

SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
by: Xuan, Wei, et al.
Published: (2025)

Balancing FP8 Computation Accuracy and Efficiency on Digital CIM via Shift-Aware On-the-fly Aligned-Mantissa Bitwidth Prediction
by: Zhao, Liang, et al.
Published: (2026)

MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors
by: You, Dean, et al.
Published: (2025)

Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case Generation
by: Ma, Ruiyang, et al.
Published: (2025)

Algorithm and Hardware Co-Design for Efficient Complex-Valued Uncertainty Estimation
by: Zhang, Zehuan, et al.
Published: (2026)

Cocco: Hardware-Mapping Co-Exploration towards Memory Capacity-Communication Optimization
by: Tan, Zhanhong, et al.
Published: (2024)

GenDRAM:Hardware-Software Co-Design of General Platform in DRAM
by: Lu, Tsung-Han, et al.
Published: (2026)

GenPairX: A Hardware-Algorithm Co-Designed Accelerator for Paired-End Read Mapping
by: Eudine, Julien, et al.
Published: (2026)

Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design
by: Pan, Tianwei, et al.
Published: (2025)

METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators
by: Wang, Zhao, et al.
Published: (2021)

FineQ: Software-Hardware Co-Design for Low-Bit Fine-Grained Mixed-Precision Quantization of LLMs
by: Xie, Xilong, et al.
Published: (2025)

ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM
by: Ku, Jonathan, et al.
Published: (2024)

PIM-FW: Hardware-Software Co-Design of All-pairs Shortest Paths in DRAM
by: Lu, Tsung-Han, et al.
Published: (2025)

STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design
by: Wang, Kainan, et al.
Published: (2025)

MixPE: Quantization and Hardware Co-design for Efficient LLM Inference
by: Zhang, Yu, et al.
Published: (2024)

SigmaQuant: Hardware-Aware Heterogeneous Quantization Method for Edge DNN Inference
by: Liu, Qunyou, et al.
Published: (2026)

Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads
by: Popovici, Doru Thom, et al.
Published: (2025)

Hardware-Software Co-Design for Event-Driven SNN Deployment on Low-Cost Neuromorphic FPGAs
by: Lee, Jiwoon, et al.
Published: (2026)

ARMOR: Robust and Efficient CNN-Based SAR ATR through Model-Hardware Co-Design
by: Wickramasinghe, Sachini, et al.
Published: (2026)

Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
by: Liu, Yuhao, et al.
Published: (2026)

HERO: Hardware-Efficient RL-based Optimization Framework for NeRF Quantization
by: Zhang, Yipu, et al.
Published: (2025)

An Efficient Sparse Hardware Accelerator for Spike-Driven Transformer
by: Li, Zhengke, et al.
Published: (2025)

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
by: Yan, Zhiyuan, et al.
Published: (2024)

DaDu-Corki: Algorithm-Architecture Co-Design for Embodied AI-powered Robotic Manipulation
by: Huang, Yiyang, et al.
Published: (2024)

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
by: Fang, Wenji, et al.
Published: (2024)

Mitigating the Bandwidth Wall via Data-Streaming System-Accelerator Co-Design
by: Liu, Qunyou, et al.
Published: (2026)

Memory-Guided Unified Hardware Accelerator for Mixed-Precision Scientific Computing
by: Wang, Chuanzhen, et al.
Published: (2026)

Cross-Layer Design of Vector-Symbolic Computing: Bridging Cognition and Brain-Inspired Hardware Acceleration
by: Du, Shuting, et al.
Published: (2025)

Aquas: Enhancing Domain Specialization through Holistic Hardware-Software Co-Optimization based on MLIR
by: Zou, Yuyang, et al.
Published: (2025)