CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
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arXiv
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| Autores principales: | , , , , , , , , , , , , , |
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| Formato: | Preprint |
| Publicado: |
2025
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| _version_ | 1866910932267958272 |
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| author | Tedeschi, Riccardo Ottavi, Gianmarco Allart, Côme Wistoff, Nils Fu, Zexin Grillotti, Filippo De Ambroggi, Fabio Guidetti, Elio Rigaud, Jean-Baptiste Potin, Olivier Coulon, Jean Roch Fuguet, César Benini, Luca Rossi, Davide |
| author_facet | Tedeschi, Riccardo Ottavi, Gianmarco Allart, Côme Wistoff, Nils Fu, Zexin Grillotti, Filippo De Ambroggi, Fabio Guidetti, Elio Rigaud, Jean-Baptiste Potin, Olivier Coulon, Jean Roch Fuguet, César Benini, Luca Rossi, Davide |
| contents | Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on the industry-supported open-source CVA6 core and its superscalar variant, CVA6S, we introduce CVA6S+, an enhanced version incorporating improved branch prediction, register renaming and enhanced operand forwarding. These optimizations enable CVA6S+ to achieve a 43.5% performance improvement over the scalar configuration and 10.9% over CVA6S, with an area overhead of just 9.30% over the scalar core (CVA6). Furthermore, we integrate CVA6S+ with the OpenHW Core-V High-Performance L1 Dcache (HPDCache) and report a 74.1% bandwidth improvement over the legacy CVA6 cache subsystem. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_03762 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture Tedeschi, Riccardo Ottavi, Gianmarco Allart, Côme Wistoff, Nils Fu, Zexin Grillotti, Filippo De Ambroggi, Fabio Guidetti, Elio Rigaud, Jean-Baptiste Potin, Olivier Coulon, Jean Roch Fuguet, César Benini, Luca Rossi, Davide Hardware Architecture Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on the industry-supported open-source CVA6 core and its superscalar variant, CVA6S, we introduce CVA6S+, an enhanced version incorporating improved branch prediction, register renaming and enhanced operand forwarding. These optimizations enable CVA6S+ to achieve a 43.5% performance improvement over the scalar configuration and 10.9% over CVA6S, with an area overhead of just 9.30% over the scalar core (CVA6). Furthermore, we integrate CVA6S+ with the OpenHW Core-V High-Performance L1 Dcache (HPDCache) and report a 74.1% bandwidth improvement over the legacy CVA6 cache subsystem. |
| title | CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2505.03762 |