In-Situ Hardware Error Detection Using Specification-Derived Petri Net Models and Behavior-Derived State Sequences
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| Main Authors: | , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866913826052505600 |
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| author | Tanaka, Tomonari Uezono, Takumi Suenaga, Kohei Hashimoto, Masanori |
| author_facet | Tanaka, Tomonari Uezono, Takumi Suenaga, Kohei Hashimoto, Masanori |
| contents | In hardware accelerators used in data centers and safety-critical applications, soft errors and resultant silent data corruption significantly compromise reliability, particularly when upsets occur in control-flow operations, leading to severe failures. To address this, we introduce two methods for monitoring control flows: using specification-derived Petri nets and using behavior-derived state transitions. We validated our method across four designs: convolutional layer operation, Gaussian blur, AES encryption, and a router in Network-on-Chip. Our fault injection campaign targeting the control registers and primary control inputs demonstrated high error detection rates in both datapath and control logic. Synthesis results show that a maximum detection rate is achieved with a few to around 10% area overhead in most cases. The proposed detectors quickly detect 48% to 100% of failures resulting from upsets in internal control registers and perturbations in primary control inputs. The two proposed methods were compared in terms of area overhead and error detection rate. By selectively applying these two methods, a wide range of area constraints can be accommodated, enabling practical implementation and effectively enhancing error detection capabilities. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2505_04108 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | In-Situ Hardware Error Detection Using Specification-Derived Petri Net Models and Behavior-Derived State Sequences Tanaka, Tomonari Uezono, Takumi Suenaga, Kohei Hashimoto, Masanori Hardware Architecture In hardware accelerators used in data centers and safety-critical applications, soft errors and resultant silent data corruption significantly compromise reliability, particularly when upsets occur in control-flow operations, leading to severe failures. To address this, we introduce two methods for monitoring control flows: using specification-derived Petri nets and using behavior-derived state transitions. We validated our method across four designs: convolutional layer operation, Gaussian blur, AES encryption, and a router in Network-on-Chip. Our fault injection campaign targeting the control registers and primary control inputs demonstrated high error detection rates in both datapath and control logic. Synthesis results show that a maximum detection rate is achieved with a few to around 10% area overhead in most cases. The proposed detectors quickly detect 48% to 100% of failures resulting from upsets in internal control registers and perturbations in primary control inputs. The two proposed methods were compared in terms of area overhead and error detection rate. By selectively applying these two methods, a wide range of area constraints can be accommodated, enabling practical implementation and effectively enhancing error detection capabilities. |
| title | In-Situ Hardware Error Detection Using Specification-Derived Petri Net Models and Behavior-Derived State Sequences |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2505.04108 |