PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM
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arXiv
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| Format: | Preprint |
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2025
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| _version_ | 1866909604645961728 |
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| author | Kubo, Tatsuya Tokuda, Daichi Qu, Lei Cao, Ting Takamaeda-Yamazaki, Shinya |
| author_facet | Kubo, Tatsuya Tokuda, Daichi Qu, Lei Cao, Ting Takamaeda-Yamazaki, Shinya |
| contents | Recently, practical analog in-memory computing has been realized using unmodified commercial DRAM modules. The underlying Processing-Using-DRAM (PUD) techniques enable high-throughput bitwise operations directly within DRAM arrays. However, the presence of inherent error-prone columns hinders PUD's practical adoption. While selectively using only error-free columns would ensure reliability, this approach significantly reduces PUD's computational throughput.
This paper presents PUDTune, a novel high-precision calibration technique for increasing the number of error-free columns in PUD. PUDTune compensates for errors by applying pre-identified column-specific offsets to PUD operations. By leveraging multi-level charge states of DRAM cells, PUDTune generates fine-grained and wide-range offset variations despite the limited available rows. Our experiments with DDR4 DRAM demonstrate that PUDTune increases the number of error-free columns by 1.81$\times$ compared to conventional implementations, improving addition and multiplication throughput by 1.88$\times$ and 1.89$\times$ respectively. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_05266 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM Kubo, Tatsuya Tokuda, Daichi Qu, Lei Cao, Ting Takamaeda-Yamazaki, Shinya Hardware Architecture Distributed, Parallel, and Cluster Computing Recently, practical analog in-memory computing has been realized using unmodified commercial DRAM modules. The underlying Processing-Using-DRAM (PUD) techniques enable high-throughput bitwise operations directly within DRAM arrays. However, the presence of inherent error-prone columns hinders PUD's practical adoption. While selectively using only error-free columns would ensure reliability, this approach significantly reduces PUD's computational throughput. This paper presents PUDTune, a novel high-precision calibration technique for increasing the number of error-free columns in PUD. PUDTune compensates for errors by applying pre-identified column-specific offsets to PUD operations. By leveraging multi-level charge states of DRAM cells, PUDTune generates fine-grained and wide-range offset variations despite the limited available rows. Our experiments with DDR4 DRAM demonstrate that PUDTune increases the number of error-free columns by 1.81$\times$ compared to conventional implementations, improving addition and multiplication throughput by 1.88$\times$ and 1.89$\times$ respectively. |
| title | PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM |
| topic | Hardware Architecture Distributed, Parallel, and Cluster Computing |
| url | https://arxiv.org/abs/2505.05266 |