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| Auteurs principaux: | , , , |
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| Format: | Preprint |
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2025
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| Accès en ligne: | https://arxiv.org/abs/2505.06096 |
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| _version_ | 1866916817701699584 |
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| author | Bush, Sam DeLorenzo, Matthew Tieu, Phat Rajendran, Jeyavijayan |
| author_facet | Bush, Sam DeLorenzo, Matthew Tieu, Phat Rajendran, Jeyavijayan |
| contents | Limitations in Large Language Model (LLM) capabilities for hardware design tasks, such as generating functional Verilog codes, have motivated various fine-tuning optimizations utilizing curated hardware datasets from open-source repositories. However, these datasets remain limited in size and contain minimal checks on licensing for reuse, resulting in potential copyright violations by fine-tuned LLMs. Therefore, we propose an evaluation benchmark to estimate the risk of Verilog-trained LLMs to generate copyright-protected codes. To minimize this risk, we present an open-source Verilog dataset, FreeSet, containing over 220k files, along with the automated dataset curation framework utilized to provide additional guarantees of fair-use Verilog data. We then execute an LLM fine-tuning framework consisting of continual pre-training, resulting in a fine-tuned Llama model for Verilog, FreeV. Our results indicate that FreeV demonstrates the smallest risk of copyright-infringement among prior works, with only a 3% violation rate. Furthermore, experimental results demonstrate improvements in Verilog generation functionality over its baseline model, improving VerilogEval pass@10 rates by over 10%. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_06096 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs Bush, Sam DeLorenzo, Matthew Tieu, Phat Rajendran, Jeyavijayan Artificial Intelligence Limitations in Large Language Model (LLM) capabilities for hardware design tasks, such as generating functional Verilog codes, have motivated various fine-tuning optimizations utilizing curated hardware datasets from open-source repositories. However, these datasets remain limited in size and contain minimal checks on licensing for reuse, resulting in potential copyright violations by fine-tuned LLMs. Therefore, we propose an evaluation benchmark to estimate the risk of Verilog-trained LLMs to generate copyright-protected codes. To minimize this risk, we present an open-source Verilog dataset, FreeSet, containing over 220k files, along with the automated dataset curation framework utilized to provide additional guarantees of fair-use Verilog data. We then execute an LLM fine-tuning framework consisting of continual pre-training, resulting in a fine-tuned Llama model for Verilog, FreeV. Our results indicate that FreeV demonstrates the smallest risk of copyright-infringement among prior works, with only a 3% violation rate. Furthermore, experimental results demonstrate improvements in Verilog generation functionality over its baseline model, improving VerilogEval pass@10 rates by over 10%. |
| title | Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs |
| topic | Artificial Intelligence |
| url | https://arxiv.org/abs/2505.06096 |