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| Main Authors: | , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2505.07514 |
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| _version_ | 1866918065298472960 |
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| author | Chu, Yanbo Zhang, Zhicai |
| author_facet | Chu, Yanbo Zhang, Zhicai |
| contents | This paper presents the design and testing of a time-stretching-based time-to-digital converter (TDC) implemented with discrete components. The TDC utilizes capacitor charging and discharging to achieve a time resolution of under 100 ps using a 100 MHz clock counter on a low-power, low-cost FPGA, achieving a time amplification factor of over 100. A two-stage time-stretching architecture is employed to reduce the conversion time to below 300 ns for a 10 ns input range. An onboard calibration system, including a pulse generation circuit, is implemented, and calibration results are presented. This system serves as a proof-of-concept platform for circuit optimization toward an ASIC implementation of a front-end TDC targeting future 4D pixel detectors at hadron colliders, with goals of sub-50 ps resolution and power consumption at the $μ$W/channel level. Additionally, the design offers a modular, low-cost solution for extracting signal arrival times with 100 ps precision in particle physics experiments, such as photoelectron timing extraction for photodetector readout in neutrino experiments. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_07514 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A two-stage time-stretching TDC with discrete components Chu, Yanbo Zhang, Zhicai Instrumentation and Detectors High Energy Physics - Experiment Nuclear Experiment This paper presents the design and testing of a time-stretching-based time-to-digital converter (TDC) implemented with discrete components. The TDC utilizes capacitor charging and discharging to achieve a time resolution of under 100 ps using a 100 MHz clock counter on a low-power, low-cost FPGA, achieving a time amplification factor of over 100. A two-stage time-stretching architecture is employed to reduce the conversion time to below 300 ns for a 10 ns input range. An onboard calibration system, including a pulse generation circuit, is implemented, and calibration results are presented. This system serves as a proof-of-concept platform for circuit optimization toward an ASIC implementation of a front-end TDC targeting future 4D pixel detectors at hadron colliders, with goals of sub-50 ps resolution and power consumption at the $μ$W/channel level. Additionally, the design offers a modular, low-cost solution for extracting signal arrival times with 100 ps precision in particle physics experiments, such as photoelectron timing extraction for photodetector readout in neutrino experiments. |
| title | A two-stage time-stretching TDC with discrete components |
| topic | Instrumentation and Detectors High Energy Physics - Experiment Nuclear Experiment |
| url | https://arxiv.org/abs/2505.07514 |