APA (7th ed.) Citation

Ding, H., Ji, H., Li, J., Chen, J., Sham, C., & Wang, Y. (2025). GDNTT: An Area-Efficient Parallel NTT Accelerator Using Glitch-Driven Near-Memory Computing and Reconfigurable 10T SRAM.

Chicago Style (17th ed.) Citation

Ding, Hengyu, Houran Ji, Jia Li, Jinhang Chen, Chin-Wing Sham, and Yao Wang. GDNTT: An Area-Efficient Parallel NTT Accelerator Using Glitch-Driven Near-Memory Computing and Reconfigurable 10T SRAM. 2025.

MLA (9th ed.) Citation

Ding, Hengyu, et al. GDNTT: An Area-Efficient Parallel NTT Accelerator Using Glitch-Driven Near-Memory Computing and Reconfigurable 10T SRAM. 2025.