MINIMALIST: switched-capacitor circuits for efficient in-memory computation of gated recurrent units
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arXiv
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| Main Authors: | , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866913834646634496 |
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| author | Billaudelle, Sebastian Kriener, Laura Moro, Filippo Torchet, Tristan Payvand, Melika |
| author_facet | Billaudelle, Sebastian Kriener, Laura Moro, Filippo Torchet, Tristan Payvand, Melika |
| contents | Recurrent neural networks (RNNs) have been a long-standing candidate for processing of temporal sequence data, especially in memory-constrained systems that one may find in embedded edge computing environments. Recent advances in training paradigms have now inspired new generations of efficient RNNs. We introduce a streamlined and hardware-compatible architecture based on minimal gated recurrent units (GRUs), and an accompanying efficient mixed-signal hardware implementation of the model. The proposed design leverages switched-capacitor circuits not only for in-memory computation (IMC), but also for the gated state updates. The mixed-signal cores rely solely on commodity circuits consisting of metal capacitors, transmission gates, and a clocked comparator, thus greatly facilitating scaling and transfer to other technology nodes.
We benchmark the performance of our architecture on time series data, introducing all constraints required for a direct mapping to the hardware system. The direct compatibility is verified in mixed-signal simulations, reproducing data recorded from the software-only network model. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_08599 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | MINIMALIST: switched-capacitor circuits for efficient in-memory computation of gated recurrent units Billaudelle, Sebastian Kriener, Laura Moro, Filippo Torchet, Tristan Payvand, Melika Hardware Architecture Artificial Intelligence Machine Learning Signal Processing Recurrent neural networks (RNNs) have been a long-standing candidate for processing of temporal sequence data, especially in memory-constrained systems that one may find in embedded edge computing environments. Recent advances in training paradigms have now inspired new generations of efficient RNNs. We introduce a streamlined and hardware-compatible architecture based on minimal gated recurrent units (GRUs), and an accompanying efficient mixed-signal hardware implementation of the model. The proposed design leverages switched-capacitor circuits not only for in-memory computation (IMC), but also for the gated state updates. The mixed-signal cores rely solely on commodity circuits consisting of metal capacitors, transmission gates, and a clocked comparator, thus greatly facilitating scaling and transfer to other technology nodes. We benchmark the performance of our architecture on time series data, introducing all constraints required for a direct mapping to the hardware system. The direct compatibility is verified in mixed-signal simulations, reproducing data recorded from the software-only network model. |
| title | MINIMALIST: switched-capacitor circuits for efficient in-memory computation of gated recurrent units |
| topic | Hardware Architecture Artificial Intelligence Machine Learning Signal Processing |
| url | https://arxiv.org/abs/2505.08599 |