Imagen de Portada

Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS

Fuente: arXiv

Guardado en:

Detalles Bibliográficos
Autores principales:	Sauter, Philippe, Benz, Thomas, Scheffler, Paul, Povišer, Martin, Gürkaynak, Frank K., Benini, Luca
Formato:	Preprint
Publicado:	2025
Materias:	Hardware Architecture
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
por: Scheffler, Paul, et al.
Publicado: (2024)

Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC
por: Sauter, Phillippe, et al.
Publicado: (2024)

Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?
por: Sauter, Philippe, et al.
Publicado: (2024)

Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon
por: Sauter, Phillippe, et al.
Publicado: (2025)

HyperCroc: End-to-End Open-Source RISC-V MCU with a Plug-In Interface for Domain-Specific Accelerators
por: Sauter, Philippe, et al.
Publicado: (2026)

Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
por: Vanoni, Axel, et al.
Publicado: (2026)

Who Checks the Checker? Enhancing Component-level Architectural SEU Fault Tolerance for End-to-End SoC Protection
por: Rogenmoser, Michael, et al.
Publicado: (2026)

HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
por: Valente, Luca, et al.
Publicado: (2022)

FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support
por: Fischer, Tim, et al.
Publicado: (2024)

Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC
por: Rogenmoser, Michael, et al.
Publicado: (2024)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET
por: Scheffler, Paul, et al.
Publicado: (2025)

Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs
por: Koenig, Cyril, et al.
Publicado: (2025)

A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
por: Benz, Thomas, et al.
Publicado: (2025)

Work-In-Progress: Accelerating Numpy With OpenBLAS For Open-Source RISC-V Chips
por: Koenig, Cyril, et al.
Publicado: (2025)

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine
por: Prasad, Arpan Suravi, et al.
Publicado: (2023)

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET
por: Paulin, Gianna, et al.
Publicado: (2024)

Fused-Tiled Layers: Minimizing Data Movement on RISC-V SoCs with Software-Managed Caches
por: Jung, Victor J. B., et al.
Publicado: (2025)

A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation
por: Valente, Luca, et al.
Publicado: (2024)

TOP: Towards Open & Predictable Heterogeneous SoCs
por: Valente, Luca, et al.
Publicado: (2024)

Chiplet-Based RISC-V SoC with Modular AI Acceleration
por: Bharadwaj, Suhas Suresh, et al.
Publicado: (2025)

Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference
por: Kumar, Vineet, et al.
Publicado: (2025)

Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience
por: Conti, Francesco, et al.
Publicado: (2024)

Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
por: Scheffler, Paul, et al.
Publicado: (2025)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
por: Garofalo, Angelo, et al.
Publicado: (2025)

SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers
por: Scheffler, Paul, et al.
Publicado: (2024)

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm
por: Rogenmoser, Michael, et al.
Publicado: (2023)

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor
por: Reinwardt, Christopher, et al.
Publicado: (2025)

NeCTAr: A Heterogeneous RISC-V SoC for Language Model Inference in Intel 16
por: Schmulbach, Viansa, et al.
Publicado: (2025)

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
por: Giorgi, Roberto, et al.
Publicado: (2025)

A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems
por: Bonet, Marc Solé i, et al.
Publicado: (2025)

FeNN-DMA: A RISC-V SoC for SNN acceleration
por: Aizaz, Zainab, et al.
Publicado: (2025)

System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check
por: Cunha, Luis, et al.
Publicado: (2026)

SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions
por: Manoni, Simone, et al.
Publicado: (2025)

ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package
por: Ottaviano, Alessandro, et al.
Publicado: (2024)

CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device
por: and, Yan-Cheng Guo, et al.
Publicado: (2025)

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications
por: Rogenmoser, Michael, et al.
Publicado: (2024)

MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI
por: M, Ajay Kumar, et al.
Publicado: (2025)

An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
por: Sekonji, Mohammad Javad, et al.
Publicado: (2026)

Where Linux Breaks Under Radiation: A Cross-Architecture Kernel-Level Characterization of Proton-Induced Failures in COTS SoCs
por: Memon, Saad, et al.
Publicado: (2025)

SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
por: Gunawardana, Kanishka, et al.
Publicado: (2026)