Scalable 28nm IC implementation of coupled oscillator network featuring tunable topology and complexity
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866909611181735936 |
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| author | Neyaz, S. Y. Ashok, A. Schiek, M. Grewing, C. Zambanini, A. van Waasen, S. |
| author_facet | Neyaz, S. Y. Ashok, A. Schiek, M. Grewing, C. Zambanini, A. van Waasen, S. |
| contents | Integrated circuit implementations of coupled oscillator networks have recently gained increased attention. The focus is usually on using these networks for analogue computing, for example for solving computational optimization tasks. For use within analog computing, these networks are run close to critical dynamics. On the other hand, such networks are also used as an analogy of transport networks such as electrical power grids to answer the question of how exactly such critical dynamic states can be avoided. However, simulating large network of coupled oscillators is computationally intensive, with specifc regards to electronic ones. We have developed an integrated circuit using integrated Phase-Locked Loop (PLL) with modifications, that allows to flexibly vary the topology as well as a complexity parameter of the network during operation. The proposed architecture, inspired by the brain, employs a clustered architecture, with each cluster containing 7 PLLs featuring programmable coupling mechanisms. Additionally, the inclusion of a RISC-V processor enables future algorithmic implementations. Thus, we provide a practical alternative for large-scale network simulations both in the field of analog computing and transport network stability research. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_10248 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Scalable 28nm IC implementation of coupled oscillator network featuring tunable topology and complexity Neyaz, S. Y. Ashok, A. Schiek, M. Grewing, C. Zambanini, A. van Waasen, S. Emerging Technologies Hardware Architecture Integrated circuit implementations of coupled oscillator networks have recently gained increased attention. The focus is usually on using these networks for analogue computing, for example for solving computational optimization tasks. For use within analog computing, these networks are run close to critical dynamics. On the other hand, such networks are also used as an analogy of transport networks such as electrical power grids to answer the question of how exactly such critical dynamic states can be avoided. However, simulating large network of coupled oscillators is computationally intensive, with specifc regards to electronic ones. We have developed an integrated circuit using integrated Phase-Locked Loop (PLL) with modifications, that allows to flexibly vary the topology as well as a complexity parameter of the network during operation. The proposed architecture, inspired by the brain, employs a clustered architecture, with each cluster containing 7 PLLs featuring programmable coupling mechanisms. Additionally, the inclusion of a RISC-V processor enables future algorithmic implementations. Thus, we provide a practical alternative for large-scale network simulations both in the field of analog computing and transport network stability research. |
| title | Scalable 28nm IC implementation of coupled oscillator network featuring tunable topology and complexity |
| topic | Emerging Technologies Hardware Architecture |
| url | https://arxiv.org/abs/2505.10248 |