Wang, Y., Sun, G., Ye, W., Qu, G., & Li, A. (2025). VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation.
Chicago Style (17th ed.) CitationWang, Yiting, Guoheng Sun, Wanghao Ye, Gang Qu, and Ang Li. VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation. 2025.
MLA (9th ed.) CitationWang, Yiting, et al. VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation. 2025.
Warning: These citations may not always be 100% accurate.