Wang, Y., Sun, G., Ye, W., Qu, G., & Li, A. (2025). VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation.
Cita Chicago Style (17a ed.)Wang, Yiting, Guoheng Sun, Wanghao Ye, Gang Qu, y Ang Li. VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation. 2025.
Cita MLA (9a ed.)Wang, Yiting, et al. VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation. 2025.
Precaución: Estas citas no son 100% exactas.