AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866913844504297472 |
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| author | Nguyen, Van Tinh Pham, Phuc Hung Le, Vu Trung Duong Pham, Hoai Luan Vu, Tuan Hai Tran, Thi Diem |
| author_facet | Nguyen, Van Tinh Pham, Phuc Hung Le, Vu Trung Duong Pham, Hoai Luan Vu, Tuan Hai Tran, Thi Diem |
| contents | The Advanced Encryption Standard (AES) is a widely adopted cryptographic algorithm essential for securing embedded systems and IoT platforms. However, existing AES hardware accelerators often face limitations in performance, energy efficiency, and flexibility. This paper presents AES-RV, a hardware-efficient RISC-V accelerator featuring low-latency AES instruction extensions optimized for real-time processing across all AES modes and key sizes. AES-RV integrates three key innovations: high-bandwidth internal buffers for continuous data processing, a specialized AES unit with custom low-latency instructions, and a pipelined system supported by a ping-pong memory transfer mechanism. Implemented on the Xilinx ZCU102 SoC FPGA, AES-RV achieves up to 255.97 times speedup and up to 453.04 times higher energy efficiency compared to baseline and conventional CPU/GPU platforms. It also demonstrates superior throughput and area efficiency against state-of-the-art AES accelerators, making it a strong candidate for secure and high-performance embedded systems. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_11880 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security Nguyen, Van Tinh Pham, Phuc Hung Le, Vu Trung Duong Pham, Hoai Luan Vu, Tuan Hai Tran, Thi Diem Hardware Architecture Cryptography and Security C.3; B.6.3; E.3 The Advanced Encryption Standard (AES) is a widely adopted cryptographic algorithm essential for securing embedded systems and IoT platforms. However, existing AES hardware accelerators often face limitations in performance, energy efficiency, and flexibility. This paper presents AES-RV, a hardware-efficient RISC-V accelerator featuring low-latency AES instruction extensions optimized for real-time processing across all AES modes and key sizes. AES-RV integrates three key innovations: high-bandwidth internal buffers for continuous data processing, a specialized AES unit with custom low-latency instructions, and a pipelined system supported by a ping-pong memory transfer mechanism. Implemented on the Xilinx ZCU102 SoC FPGA, AES-RV achieves up to 255.97 times speedup and up to 453.04 times higher energy efficiency compared to baseline and conventional CPU/GPU platforms. It also demonstrates superior throughput and area efficiency against state-of-the-art AES accelerators, making it a strong candidate for secure and high-performance embedded systems. |
| title | AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security |
| topic | Hardware Architecture Cryptography and Security C.3; B.6.3; E.3 |
| url | https://arxiv.org/abs/2505.11880 |