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AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security

Fuente: arXiv

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Bibliographic Details
Main Authors:	Nguyen, Van Tinh, Pham, Phuc Hung, Le, Vu Trung Duong, Pham, Hoai Luan, Vu, Tuan Hai, Tran, Thi Diem
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Cryptography and Security C.3; B.6.3; E.3
Online Access:	Acceder al recurso
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