Addressing memory bandwidth scalability in vector processors for streaming applications
Fuente:
arXiv
Saved in:
| Main Authors: | Altayo, Jordi, Delestrac, Paul, Novo, David, Yang, Simey, Bhattacharjee, Debjyoti, Catthoor, Francky |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
CIS: Composable Instruction Set for Data Streaming Applications
by: Yang, Yu, et al.
Published: (2024)
by: Yang, Yu, et al.
Published: (2024)
Architectural Classification of XR Workloads: Cross-Layer Archetypes and Implications
by: Shi, Xinyu, et al.
Published: (2026)
by: Shi, Xinyu, et al.
Published: (2026)
Optimizing GEMM for Energy and Performance on Versal ACAP Architectures
by: Papalamprou, Ilias, et al.
Published: (2025)
by: Papalamprou, Ilias, et al.
Published: (2025)
PIMfused: Near-Bank DRAM-PIM with Fused-layer Dataflow for CNN Data Transfer Optimization
by: Yang, Simei, et al.
Published: (2025)
by: Yang, Simei, et al.
Published: (2025)
Improving the Representativeness of Simulation Intervals for the Cache Memory System
by: Bueno, Nicolas, et al.
Published: (2024)
by: Bueno, Nicolas, et al.
Published: (2024)
Calibrating DRAMPower Model for HPC: A Runtime Perspective from Real-Time Measurements
by: Shi, Xinyu, et al.
Published: (2024)
by: Shi, Xinyu, et al.
Published: (2024)
pHNSW: PCA-Based Filtering to Accelerate HNSW Approximate Nearest Neighbor Search
by: Li, Zheng, et al.
Published: (2026)
by: Li, Zheng, et al.
Published: (2026)
FlexVector: A SpMM Vector Processor with Flexible VRF for GCNs on Varying-Sparsity Graphs
by: Li, Bohan, et al.
Published: (2026)
by: Li, Bohan, et al.
Published: (2026)
Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes
by: Ruotolo, Lorenzo, et al.
Published: (2025)
by: Ruotolo, Lorenzo, et al.
Published: (2025)
Decoupled Control Flow and Data Access in RISC-V GPGPUs
by: Sarda, Giuseppe M., et al.
Published: (2025)
by: Sarda, Giuseppe M., et al.
Published: (2025)
Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis
by: Sarda, Giuseppe M., et al.
Published: (2024)
by: Sarda, Giuseppe M., et al.
Published: (2024)
Full-stack evaluation of Machine Learning inference workloads for RISC-V systems
by: Bhattacharjee, Debjyoti, et al.
Published: (2024)
by: Bhattacharjee, Debjyoti, et al.
Published: (2024)
Linear Decomposition of the Majority Boolean Function using the Ones on Smaller Variables
by: Chattopadhyay, Anupam, et al.
Published: (2025)
by: Chattopadhyay, Anupam, et al.
Published: (2025)
'1'-bit Count-based Sorting Unit to Reduce Link Power in DNN Accelerators
by: Han, Ruichi, et al.
Published: (2026)
by: Han, Ruichi, et al.
Published: (2026)
A complete discussion on fully reconfigurable, digital, scalable, graph and sparsity-aware near-memory accelerator for graph neural networks
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)
by: Raman, Siddhartha Raman Sundara, et al.
Published: (2026)
RISC-V processor enhanced with a dynamic micro-decoder unit
by: Pottier, Juliette, et al.
Published: (2024)
by: Pottier, Juliette, et al.
Published: (2024)
EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques
by: Canpolat, Oğuzhan, et al.
Published: (2025)
by: Canpolat, Oğuzhan, et al.
Published: (2025)
TaiBai: A fully programmable brain-inspired processor with topology-aware efficiency
by: Li, Qianpeng, et al.
Published: (2025)
by: Li, Qianpeng, et al.
Published: (2025)
The Landscape of Compute-near-memory and Compute-in-memory: A Research and Commercial Overview
by: Khan, Asif Ali, et al.
Published: (2024)
by: Khan, Asif Ali, et al.
Published: (2024)
CADC: Crossbar-Aware Dendritic Convolution for Efficient In-memory Computing
by: Dong, Shuai, et al.
Published: (2025)
by: Dong, Shuai, et al.
Published: (2025)
PC-Indexed Data Address Translation
by: Murthy, Shyam, et al.
Published: (2024)
by: Murthy, Shyam, et al.
Published: (2024)
PIVOT- Input-aware Path Selection for Energy-efficient ViT Inference
by: Moitra, Abhishek, et al.
Published: (2024)
by: Moitra, Abhishek, et al.
Published: (2024)
Versatile silicon integrated photonic processor: a reconfigurable solution for next-generation AI clusters
by: Zhu, Ying, et al.
Published: (2025)
by: Zhu, Ying, et al.
Published: (2025)
Towards Forever Access for Implanted Brain-Computer Interfaces
by: Ugur, Muhammed, et al.
Published: (2024)
by: Ugur, Muhammed, et al.
Published: (2024)
Swapping-Centric Neural Recording Systems
by: Ugur, Muhammed, et al.
Published: (2024)
by: Ugur, Muhammed, et al.
Published: (2024)
Topkima-Former: Low-energy, Low-Latency Inference for Transformers using top-k In-memory ADC
by: Dong, Shuai, et al.
Published: (2024)
by: Dong, Shuai, et al.
Published: (2024)
Emerging memory technologies at room/cryogenic temperature
by: Raman, Siddhartha Raman Sundara
Published: (2026)
by: Raman, Siddhartha Raman Sundara
Published: (2026)
PIMSYN: Synthesizing Processing-in-memory CNN Accelerators
by: Li, Wanqian, et al.
Published: (2024)
by: Li, Wanqian, et al.
Published: (2024)
GeneTEK: Low-power, high-performance and scalable FPGA architecture for exact unit-cost edit distance
by: Espinosa, Elena, et al.
Published: (2025)
by: Espinosa, Elena, et al.
Published: (2025)
CarbonClarity: Understanding and Addressing Uncertainty in Embodied Carbon for Sustainable Computing
by: Chen, Xuesi, et al.
Published: (2025)
by: Chen, Xuesi, et al.
Published: (2025)
DaPPA: A Data-Parallel Programming Framework for Processing-in-Memory Architectures
by: Oliveira, Geraldo F., et al.
Published: (2023)
by: Oliveira, Geraldo F., et al.
Published: (2023)
IMSSA: Deploying modern state-space models on memristive in-memory compute hardware
by: Siegel, Sebastian, et al.
Published: (2024)
by: Siegel, Sebastian, et al.
Published: (2024)
Virtual memory for real-time systems using hPMP
by: Walluszik, Konrad, et al.
Published: (2025)
by: Walluszik, Konrad, et al.
Published: (2025)
DiffAxE: Diffusion-driven Hardware Accelerator Generation and Design Space Exploration
by: Ghosh, Arkapravo, et al.
Published: (2025)
by: Ghosh, Arkapravo, et al.
Published: (2025)
FeNN: A RISC-V vector processor for Spiking Neural Network acceleration
by: Aizaz, Zainab, et al.
Published: (2025)
by: Aizaz, Zainab, et al.
Published: (2025)
ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
by: Petrolo, Vincenzo, et al.
Published: (2025)
by: Petrolo, Vincenzo, et al.
Published: (2025)
MatrixFlow: System-Accelerator co-design for high-performance transformer applications
by: Liu, Qunyou, et al.
Published: (2025)
by: Liu, Qunyou, et al.
Published: (2025)
A methodology to automatically optimize dynamic memory managers applying grammatical evolution
by: Risco-Martín, José L., et al.
Published: (2024)
by: Risco-Martín, José L., et al.
Published: (2024)
NDPage: Efficient Address Translation for Near-Data Processing Architectures via Tailored Page Table
by: Jiang, Qingcai, et al.
Published: (2025)
by: Jiang, Qingcai, et al.
Published: (2025)
Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs
by: Koenig, Cyril, et al.
Published: (2025)
by: Koenig, Cyril, et al.
Published: (2025)
Similar Items
-
CIS: Composable Instruction Set for Data Streaming Applications
by: Yang, Yu, et al.
Published: (2024) -
Architectural Classification of XR Workloads: Cross-Layer Archetypes and Implications
by: Shi, Xinyu, et al.
Published: (2026) -
Optimizing GEMM for Energy and Performance on Versal ACAP Architectures
by: Papalamprou, Ilias, et al.
Published: (2025) -
PIMfused: Near-Bank DRAM-PIM with Fused-layer Dataflow for CNN Data Transfer Optimization
by: Yang, Simei, et al.
Published: (2025) -
Improving the Representativeness of Simulation Intervals for the Cache Memory System
by: Bueno, Nicolas, et al.
Published: (2024)