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| Hauptverfasser: | , , |
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| Format: | Preprint |
| Veröffentlicht: |
2025
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| Schlagworte: | |
| Online-Zugang: | https://arxiv.org/abs/2505.18353 |
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| _version_ | 1866916756362100736 |
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| author | Babaee, Ramin Gharan, Shahab Oveis Bouchard, Martin |
| author_facet | Babaee, Ramin Gharan, Shahab Oveis Bouchard, Martin |
| contents | We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random current mismatches. Unlike binary, thermometer-coded, and segmented DACs, the current weights of the proposed architecture are not an integer power of 2 or any other integer number. We present a heuristic algorithm for a static mapping of DAC input codewords into corresponding DAC switches. High-level Matlab simulations are performed to illustrate the static performance improvement over the segmented structure. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2505_18353 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Current-Steering DAC Architecture Design for Amplitude Mismatch Error Minimization Babaee, Ramin Gharan, Shahab Oveis Bouchard, Martin Signal Processing We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random current mismatches. Unlike binary, thermometer-coded, and segmented DACs, the current weights of the proposed architecture are not an integer power of 2 or any other integer number. We present a heuristic algorithm for a static mapping of DAC input codewords into corresponding DAC switches. High-level Matlab simulations are performed to illustrate the static performance improvement over the segmented structure. |
| title | Current-Steering DAC Architecture Design for Amplitude Mismatch Error Minimization |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2505.18353 |